Zilog Z80230 - Manual (Page 26)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
19
Z80X30 Write Cycle
Z80X30 Interrupt Acknowledge Cycle Timing
The interrupt acknowledge cycle timing for the Z80X30 is displayed in Figure on page 20. The
address on AD7-AD0 and the state of /CS0 and /INTACK are latched by the rising edge of /AS.
However, if /INTACK is Low, the address, /CS0, CS1 and R//W are ignored for the duration of the
interrupt acknowledge cycle.
Address Data Valid
/AS
/CS0
/INTACK
AD7 - AD0
R//W
CS1
/DS