Zilog Z80230 User Manual
Page 257
SCC/ESCC
User Manual
UM010903-0515
Application Notes
250
AN0097: The Zilog® Datacom Family with the 80186 CPU
Abstract
Zilog’s customers need a way to evaluate its serial communications controllers with a central
CPU. This application note describes how Zilog’s Datacom family interfaces and communicates
with Intel’s 80186 CPU on this evaluation board. The evaluation board helps you to evaluate
Zilog’s data communication controllers in an Intel environment.
The most advanced and complex component of the serial family is the Integrated Universal Serial
Controller (IUSC). This application note highlights how the IUSC adapts to the 80186 CPU with
minimum difficulty and maximum bus and functional flexibility.
General Description
The evaluation board includes the following hardware:
•
Intel 80186 Integrated 16-Bit Microprocessor.
•
Zilog Z16C32 Integrated Universal
Serial Controller (IUSC
TM
).
•
Zilog Z16C33 Monochannel Universal
Serial Controller (MUSC
TM
).
•
Zilog Z16C35 Integrated Serial
Communications Controller (ISCC
TM
).
•
Zilog Z85230 Enhanced Serial
Communications Controller (ESCC
TM
)
or SCC.
•
Two 28-pin EPROM sockets, suitable
for 2764’s through 27512’s.
•
Six 32-pin (or 28-pin) SRAM sockets, suitable for 32K x 8 or 128K x 8 devices.
•
Four Altera EPLD circuits comprising the glue logic. See Figure through Figure on
•
RS-232 and RS-422 line drivers and receivers.
•
Pin headers for configuring and interconnecting the above hardware to serial applications.
All signals with an overline are active Low. For example, in R/W (WRITE is active Low); in
R/W (Read is active Low).
Note: