Zilog Z80230 - Manual (Page 125)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
118
Modem Control signals related to SDLC Transmit
There are two modem control signals associated with the transmitter provided by the SCC. The /
RTS pin is a simple output that carries the inverted state of the RTS bit (D1) in WR5. The /CTS
pin is ordinarily a simple input to the CTS bit in RR0. However, if Auto Enables mode is selected,
this pin becomes an enable for the transmitter. If Auto Enables is on and the /CTS pin is High, the
transmitter is disabled. The transmitter is enabled if the /CTS pin is Low.
ESCC Enhancements for SDLC Transmit
The ESCC has the following enhancements available in the SDLC mode of operation which can
reduce CPU overhead dramatically. These features are:
• Deeper Transmit FIFO (Four Bytes)
• CRC takes priority over the data
• Auto EOM Reset (WR7' bit D1)
• Auto Tx Flag (WR7' bit D0)
• Auto RTS Deactivation (WR7' bit D2)
• TxD pin forced High after closing flag in NRZI mode
Deeper Transmit FIFO:
The ESCC has a four byte deep Transmit FIFO, where the NMOS/
CMOS version has a one byte deep transmit buffer. To maximize the system’s performance, there
are two modes of operation for the transmit interrupt and DMA request, which are programmed by
bit D5 of WR7'.
The ESCC sets WR7' bit D5 to 1 following a hardware or software reset. This is done to provide
maximum compatibility with existing SCC designs. In this mode, the ESCC generates the transmit
buffer empty interrupt and DMA transmit request when the Transmit FIFO is completely empty.
Interrupt driven systems can maximize efficiency by writing four bytes for each entry into the
Transmit Interrupt Service Routine (TISR), filling the Transmit FIFO without having to check any
status bits. Since the TBE status bit is set if the entry location of the FIFO is empty, this bit can be
tested at any time if more data is written. Applications requiring software compatibility with the
NMOS/CMOS version can test the TBE bit in the TISR after each data write to determine if more
data can be written. This allows a system with an ESCC to minimize the number of transmit inter-
rupts, but not overflow SCC systems. DMA driven systems originally designed for the SCC can
use this mode to reassert the DMA request for more data after the first byte written to the FIFO is
loaded to the Transmit Shift register. Consequently, any subsequent re-assertion allows the DMA
sufficient time to detect the High-to-Low edge.
If WR7' D5 is reset to 0, the transmit buffer empty interrupt and DMA request are generated when
the entry location of the FIFO is empty. Therefore, if more than one byte is required to fill the
entry location of the FIFO, the ESCC generates interrupts or DMA requests until the entry loca-
tion of the FIFO is filled. The transmit DMA request pin (either /WAIT//REQ or /DTR//REQ)
goes inactive after each data transfer, then goes active again and, consequently, generates a High-
to-Low edge for each byte. Edge triggered DMA should be enabled before the transmit DMA