Zilog Z80230 - Manual (Page 6)

SCC/ESCC
User Manual
UM010903-0515
vi
Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode
Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Write Register 2 (Interrupt Vector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Write Register 3 (Receive Parameters and Control) . . . . . . . . . . . . . . . 148
Write Register 4 (Transmit/Receive Miscellaneous Parameters 
and Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Write Register 5 (Transmit Parameters and Controls) . . . . . . . . . . . . . 152
Write Register 6 (Sync Characters or SDLC Address Field) 154
Write Register 7 (Sync Character or SDLC Flag) . . . . . . . . . . . . . . . . . 155
Write Register 7 Prime (ESCC only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Write Register 7 Prime (85C30 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Write Register 8 (Transmit Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Write Register 9 (Master Interrupt Control) . . . . . . . . . . . . . . . . . . . . . . 159
Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) . . 162
Write Register 11 (Clock Mode Control) . . . . . . . . . . . . . . . . . . . . . . . . 165
Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) 167
Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) 169
Write Register 14 (Miscellaneous Control Bits) . . . . . . . . . . . . . . . . . . . 169
Write Register 15 (External/Status Interrupt Control) . . . . . . . . . . . . . . 172
Read Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Read Register 0 (Transmit/Receive Buffer Status and External Status) 174
Read Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Read Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Read Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Read Register 4 (ESCC and 85C30 Only) . . . . . . . . . . . . . . . . . . . . . . 182
Read Register 5 (ESCC and 85C30 Only) . . . . . . . . . . . . . . . . . . . . . . 182
Read Register 6 (Not on NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Read Register 7 (Not on NMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Read Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Read Register 9 (ESCC and 85C30 Only) . . . . . . . . . . . . . . . . . . . . . . 184
Read Register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Read Register 11 (ESCC and 85C30 Only) . . . . . . . . . . . . . . . . . . . . . 186
Read Register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Read Register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Read Register 14 (ESCC and 85C30 Only) . . . . . . . . . . . . . . . . . . . . . 187
Read Register 15 187
Application Notes188
Interfacing Z80® CPUs to the Z8500 Peripheral Family . . . . . . . . . . . . . . . 188
AN0096: The Z180 Interfaced with the SCC at 10 MHz . . . . . . . . . . . . . . . 210
AN0097: The Zilog® Datacom Family with the 80186 CPU. . . . . . . . . . . . . 250