Zilog Z80230 - Manual (Page 177)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
170
Bits D7-D5: Digital Phase-Locked Loop Command Bits.
These three bits encode the eight commands for the Digital Phase-Locked Loop. A channel or
hardware reset disables the DPLL, resets the missing clock latches, sets the source to the /RTxC
pin and selects NRZI mode. The Enter Search Mode command enables the DPLL after a reset.
Null Command (000).
This command has no effect on the DPLL.
Enter Search Mode Command (001).
Issuing this command causes the DPLL to enter the Search
mode, where the DPLL searches for a locking edge in the incoming data stream. The action taken
by the DPLL upon receipt of this command depends on the operating mode of the DPLL.
In NRZI mode, the output of the DPLL is High while the DPLL is waiting for an edge in the
incoming data stream. After the Search mode is entered, the first edge the DPLL sees is assumed
to be a valid data edge, and the DPLL begins the clock recovery operation from that point. The
DPLL clock rate must be 32x the data rate in NRZI mode. Upon leaving the Search mode, the first
sampling edge of the DPLL occurs 16 of these 32x clocks after the first data edge, and the second
sampling occurs 48 of these 32x clocks after the first data edge. Beyond this point, the DPLL
begins normal operation, adjusting the output to remain in sync with the incoming data.
In FM mode, the output of the DPLL is Low while the DPLL is waiting for an edge in the incom-
ing data stream. The first edge the DPLL detects is assumed to be a valid clock edge. For this to be
the case, the line must contain only clock edges; i.e. with FM1 encoding, the line must be continu-
ous 0s. With FM0 encoding the line must be continuous 1s, whereas Manchester encoding requires
alternating 1s and 0s on the line. The DPLL clock rate must be 16 times the data rate in FM mode.
The DPLL output causes the receiver to sample the data stream in the nominal center of the two
halves of the bit to decide whether the data was a 1 or a 0.
After this command is issued, as in NRZI mode, the DPLL starts sampling immediately after the
first edge is detected. (In FM mode, the DPLL examines the clock edge of every other bit to decide
what correction must be made to remain in sync.) If the DPLL does not see an edge during the
expected window, the one clock missing bit in RR10 is set. If the DPLL does not see an edge after
two successive attempts, the two clocks missing bits in RR10 are set and the DPLL automatically
enters the Search mode. This command resets both clocks missing latches.
Reset Clock Missing Command (010).
Issuing this command disables the DPLL, resets the clock
missing latches in RR10, and forces a continuous Search mode state.
Disable DPLL Command (011).
Issuing this command disables the DPLL, resets the clock miss-
ing latches in RR10, and forces a continuous Search mode state.
Set Source to BRG Command (100).
Issuing this command forces the clock for the DPLL to
come from the output of the BRG.
Set Source to /RTxC Command (101).
Issuing the command forces the clock for the DPLL to
come from the /RTxC pin or the crystal oscillator, depending on the state of the XTAL/no XTAL
bit in WR11. This mode is selected by a channel or hardware reset.