Zilog Z80230 User Manual
Page 270
SCC/ESCC
User Manual
UM010903-0515
Application Notes
263
•
D7-D6 are 11 to allow the DMA controllers to do either 16-bit transfers, or alternating
byte transfers on AD7-AD0 for even-addressed bytes and on AD15-AD8 for odd-
addressed bytes. This is compatible with 80186 byte ordering.
•
D5-D4 of the data are 11 to select double-pulsed mode for the IUSC’s INTACK input.
•
D3 of the data is 0 to select open-drain mode on the IUSC’s BUSREQ pin. The board’s
control logic also drives this signal Low when the ISCC asserts its Bus Request output.
•
D2 of the data is 1 to tell the IUSC that the data bit is 16 bits wide.
•
D1 of the data is 1 to select open-drain mode on the IUSC’s INT pin which is OR-tied with
the interrupt request from the (E)SCC.
•
D0 of the data is 1 to select Shift Right Address Mode, so that the IUSC subsequently
takes register addressing from the AD6-AD0 lines rather than from AD7-AD1.
•
The fact that the IUSC’s internal logic sees activity on its AS pin, which is inverted from
the 80186’ ALE signal, automatically conditions it for a multiplexed Address/Data bus.
Given that the BCR is written as described above, the IUSC slave mode address map is as listed in
While the ESCC and ISCC can drive their Baud Rate Generators from their PCLK inputs, the
IUSC cannot perform the same from its CLK input. The 80186 clock output SYSCLK is brought
to Pins 7 of J9, J10, and J12 at which point it can be jumpered to pin 9 or 8 so that it is routed to
the TxC or RxC pin of the device.
Since the IUSC contains its own DMA channels, its RxREQ and TxREQ have no dedicated func-
tion. They can be used for Request to Send and Data Terminal Ready. The two signals are lightly
pulled up to allow for the fact that they are not driven after Reset.
Serial Interfacing
The serial I/O pins of the four serial controllers are connected to the six connector blocks labelled
J5 through J10. In addition, the port pins of the IUSC are connected to the J11 connector block and
the port pins of an MUSC or the B channel of a USC are connected to J12. The connector blocks
IUSC Slave Mode Address Map
Starting Address
Ending Address
Registers Accessed
(PBA)+512
(PBA)+575
16-bit access to IUSC Transmit DMA Registers
(PBA)+576
(PBA)+639
8-bit access to IUSC Transmit DMA Registers
(PBA)+640
(PBA)+703
16-bit access to IUSC Receive DMA Registers
(PBA)+704
(PBA)+767
8-bit access to IUSC Receive DMA Registers
(PBA)+768
(PBA)+831
16-bit access to IUSC Serial Controller Registers
(PBA)+832
(PBA)+895
16-bit access to IUSC Serial Controller Registers