Zilog Z80230 User Manual
Page 268
SCC/ESCC
User Manual
UM010903-0515
Application Notes
261
Jumper block J29 provides the same connection-variability for the RxREQ and TxREQ outputs of
Channel B of a USC.
Since the 80186’s channels are not capable of fly-by operation, the (M)USC’s RxACK and
TxACK pins have no dedicated function. They can be used for Request to Send and Data Terminal
Ready. The two signals are lightly pulled up since they are not driven after Reset.
The (M)USC can be programmed using 16-bit data on the AD15-AD0 lines or 8-bit data on
AD15-AD8 and AD7-AD0. It makes the distinction between 8-bit and 16-bit operations as part of
its address map rather than through a control input. The PS pin of an MUSC, or the A/B pin of a
USC, is connected to a latched version of the 80186 A7. The D/C pin of the (M)USC is grounded.
The overall address range of the (M)USC is 256 Bytes, between (PBA)+256 and (PBA)+511.
The first write to this address range, after a Reset, implicitly writes the (M)USC Bus Configura-
tion Register (BCR). To match the rest of the board’s hardware, the first write must be 16-bit write,
storing the hex value
0007
at any address in the second half of the (M)USC’s range [any address
in (PBA)+384 through 510, that is, in the A channel of a USC]. Details of this transaction are as
follows:
•
The High on the PS or A/B input, which is connected to A7, selects the WAIT protocol on
the WAIT/RDY pin, corresponding to how the 80186 works.
•
The MSB of the data (D15) is 0 because a separate non-multiplexed address is not wired to
pins AD13:8 of the (M)USC.
•
Bits 14-3 are required to be all zeros by the (M)USC internal logic.
•
D2 of the data is 1 to tell the (M)USC that the data bus is 16 bits wide.
•
D1 of the data is 1 to select double-pulsed mode for the (M)USC’s INTACK input. This is
how the 80186 CPU functions.
•
D0 of the data is 1 to select Shift Right Address mode so that the (M)USC subsequently
takes register addressing from the AD6-AD0 lines rather than from AD7-AD1.
•
The fact that the (M)USC’s internal logic sees activity on its AS pin, which is inverted
from the 80186’ ALE signal, automatically conditions it for a multiplexed Addresses/Data
bus.
Given that the BCR is written as described above, the (M)USC address map is as listed in Table .
(M)USC Address Map
Starting Address
Ending Address
Registers Accessed
(PBA)+256
(PBA)+319
16-bit access to (M)USC registers or USC Channel B Registers
(PBA)+320
(PBA)+383
8-bit access to (M)USC registers or USC Channel B Registers
(PBA)+384
(PBA)+447
16-bit access to (M)USC registers or USC Channel A Registers