Zilog Z80230 User Manual
Page 184
SCC/ESCC
User Manual
UM010903-0515
Register Descriptions
177
If the DCD IE bit in WR15 is set, this bit indicates the state of the /DCD pin the last time the
Enabled External/Status bits changed. Any transition on the /DCD pin, while no interrupt is pend-
ing, latches the state of the /DCD pin and generates an External/Status interrupt. Any odd number
of transitions on the /DCD pin while another External/Status interrupt condition. If the DCD IE is
reset, this bit merely reports the current, unlatched state of the /DCD pin.
Bit 2: TX Buffer Empty status
This bit is set to 1 when the transmit buffer is empty. It is reset while the CRC is sent in a synchro-
nous or SDLC mode and while the transmit buffer is full. The bit is reset when a character is
loaded into the transmit buffer.
On the ESCC, the status of this bit is not related to the Transmit Interrupt Status or the state of
WR7' bit D5, but it shows the status of the entry location of the Transmit FIFO. This means more
data can be written without being overwritten. This bit is set to 1 when the entry location of the
Transmit FIFO is empty. It is reset when a character is loaded into the entry location of the Trans-
mit FIFO.
This bit is always in the set condition after a hardware or channel reset.
For more information on this bit, see
Transmit Interrupts and Transmit Buffer Empty Bit
Bit 1: Zero Count status
If the Zero Count interrupt Enable bit is set in WR15, this bit is set to one while the counter in the
baud rate generator is at the count of zero. If there is no other External/Status interrupt condition
pending at the time this bit is set, an External/Status interrupt is generated. However, if there is
another External/Status interrupt pending at this time, no interrupt is initiated until interrupt ser-
vice is complete. If the Zero Count condition does not persist beyond the end of the interrupt ser-
vice routine, no interrupt is generated. This bit is not latched High, even though the other External/
Status latches close as a result of the Low-to-High transition on ZC. The interrupt routine checks
the other External/Status conditions for changes. If none changed, ZC was the source. In polled
applications, check the IP bit in RR3A for a status change and then proceed as in the interrupt ser-
vice routine.
Bit 0: Receive Character Available
This bit is set to 1 when at least one character is available in the receive data FIFO. It is reset when
the receive data FIFO is completely empty. A channel or hardware reset empties the receive data
FIFO.
On the ESCC, the status of this bit is independent of WR7' bit D3.
For details on this bit, see