Zilog Z80230 - Manual (Page 180)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
173
On the CMOS version, bits D2 and D0 are reserved. On the NMOS version, bit D2 is reserved.
These reserved bits should be written as 0s.
Write Register 15
Bit 7: Brea/Abort Interrupt Enable
If this bit is set to 1, a change in the Break/Abort status of the receiver causes an External/Status
interrupt. This bit is set by a channel or hardware reset.
Bit 6: Transmit Underrun/EOM Interrupt Enable
If this bit is set to 1, a change of state by the Tx Under-run/EOM latch in the transmitter causes an
External/Status interrupt. This bit is set to 1 by a channel or hardware reset.
Bit 5: CTS Interrupt Enable
If this bit is set to 1, a change of state on the /CTS pin causes an External/Status Interrupt. This bit
is set by a channel or hardware reset.
Bit 4: SYNC/Hunt Interrupt Enable
If this bit is set to 1, a change of state on the /SYNC pin causes an External/Status interrupt in
Asynchronous mode, and a change of state in the Hunt bit in the receiver causes and External/Sta-
tus interrupt in synchronous modes. This bit is set by a channel or hardware reset.
Bit 3: DCD Interrupt Enable
If this bit is set to 1, a change of state on the /DCD pin causes an External/Status interrupt. This bit
is set by a channel or hardware reset.
Bit 2: Status FIFO Enable control bit (CMOS/ESCC)
If this bit is set and if the CMOS/ESCC is in the SDLC/HDLC Mode, status (five bits from Read
Register 1: Residue, Overrun, and CRC Error) and fourteen bits of byte count are held in the Sta-
tus FIFO until read. Status information for up to ten frames can be stored. If this bit is reset (0) or
if the CMOS/ESCC is not in the SDLC/HDLC Mode, the FIFO is not operational and status infor-
D7 D6 D5 D4 D3 D2 D1 D0
Write Register 15
WR7' SDLC Feature Enable
(Reserved on NMOS/CMOS)
Zero Count IE
SDLC FIFO Enable (Reserved on NMOS)
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE