Zilog Z80230 User Manual
Page 116
SCC/ESCC
User Manual
UM010903-0515
Data Communication Modes
109
After eight-bit times, B is loaded into the receive data FIFO. The CRC remains disabled even
though somewhere during the next eight bit times the processor reads B and enables the CRC. At
the end of this eight-bit time, B is in the 8-bit delay and C is in the receive shift register.
Character C is loaded into the receive data FIFO and at the same time the CRC checker becomes
enabled. During the next eight-bit time, the processor reads C and since the CRC is enabled within
this period, the SCC has calculated the CRC on B, character C is the 8-bit delay, and D is in the
Receive Shift register. D is then loaded into the receive data FIFO and at some point during the
next eight-bit time the processor reads D and disables the CRC. At the end of these eight-bit times,
the CRC has been calculated on C, character D is in the 8-bit delay, and E is in the Receive Shift
register.
Now E is loaded into the receive data FIFO. During the next eight-bit time, the processor reads E
and enables the CRC. During this time E shifts into the 8-bit delay, F enters the Receive Shift reg-
ister and the CRC is not being calculated on D. After these eight-bit times have elapsed, E is in the
8-bit delay, and F is in the Receive Shift register. Now F is transferred to the receive data FIFO and
the CRC is enabled. During the next eight-bit times, the processor reads F and leaves the CRC
enabled. The processor detects that this is the last character in the message and prepares to check
the result of the CRC computation. However, another sixteen bit-times are required before the
CRC has been calculated on all of character F.
At the end of eight-bit times, F is in the 8-bit delay and G is in the Receive Shift register. At this
time, it is transferred to the receive data FIFO. Character G is read and discarded by the processor.
Eight-bit times later, H is also transferred to the receive data FIFO. The result of a CRC calcula-
tion is latched in to the Receive Error FIFO at the same time as data is written to the Receive Data
FIFO. Thus, the CRC result through character F accompanies character H in the FIFO and will be
valid in RR1 until character H is read from the Receive Data FIFO. The CRC checker is disabled
and reset at any time after character H is transferred to the Receive Data FIFO. Recall, however,
that internally the CRC is not disabled until after this occurs. A better alternative is to place the
receiver in Hunt mode, which automatically disables and resets the CRC checker. See
condensed description.
Modem Controls.
Up to two modem control signals associated with the receiver are available in
Synchronous modes: /DTR//REQ and /DCD. The /DTR//REQ pin carries the inverted state of the
DTR bit (D7) in WR5 unless this pin has been programmed to carry a DMA Request on Transmit
signal. The /DCD pin is ordinarily a simple input to the DCD bit in RR0. However, if the Auto
Enables mode is selected by setting D5 of WR3 to 1, this pin becomes an enable for the receiver.
Therefore, if Auto Enables is ON and the /DCD pin is High, the receiver is disabled; while the /
DCD pin is Low, the receiver is enabled.
Note that with Auto Enables mode enabled, when /DCD goes inactive, the receiver stops immedi-
ately and the character being assembled is lost.
Initialization.
The initialization sequence for the receiver in character-oriented mode is WR4 first,
to select the mode, then WR10 to modify it if necessary; WR6 and WR7 to program the sync char-
acters; WR3 and WR5 to select the various options. At this point the other registers are initialized
as necessary. When all this is completed, the receiver is enabled by setting bit D0 of WR3 to a one.