Zilog Z80230 - Manual (Page 168)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
161
This bit is reserved on NMOS, and always writes as 0.
Bit 4: Status High//Status Low control bit
This bit controls which vector bits the SCC modifies to indicate status. When set to 1, the SCC
modifies bits V6, V5, and V4 according to Table . When set to 0, the SCC modifies bits V1, V2,
and V3. This bit controls status in both the vector returned during an interrupt acknowledge cycle
and the status in RR2B. This bit is reset by a hardware reset.
Bit 3: Master Interrupt Enable
This bit is set to 1 to globally enable interrupts, and cleared to zero to disable interrupts. Clearing
this bit to zero forces the IEO pin to follow the state of the IEI pin unless there is an IUS bit set in
the SCC. No IUS bit is set after the MIE bit is cleared to zero. This bit is reset by a hardware reset.
Bit 2: Disable Lower Chain control bit
The Disable Lower Chain bit is used by the CPU to control the interrupt daisy chain. Setting this
bit to 1 forces the IEO pin Low, preventing lower priority devices on the daisy chain from request-
ing interrupts. This bit is reset by a hardware reset.
Bit 1: No Vector select bit
The No Vector bit controls whether or not the SCC responds to an interrupt acknowledge cycle.
This is done by placing a vector on the data bus if the SCC is the highest priority device requesting
an interrupt. If this bit is set, no vector is returned; i.e., AD7-AD0 remains tri-stated during an
interrupt acknowledge cycle, even if the SCC is the highest priority device requesting an interrupt.
Bit 0: Vector Includes Status control bit
Interrupt Vector Modification
V3 V2 V1 Status High/Status Low =0
V4 V5 V6 Status High/Status Low =1
0 0 0 Ch B Transmit Buffer Empty
0 0 1 Ch B External/Status Change
0 1 0 Ch B Receive Char. Available
0 1 1 Ch B Special Receive Condition
1 0 0 Ch A Transmit Buffer Empty
1 0 1 Ch A External/Status Change
1 1 0 Ch A Receive Char. Available
1 1 1 Ch A Special Receive Condition