Zilog Z80230 - Manual (Page 63)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
56
External/Status Interrupts
Each channel has six external/status interrupt conditions: BRG Zero Count, Data Carrier Detect,
Sync/Hunt, Clear to Send, Tx Underrun/EOM, and Break/Abort. The master enable for external/
status interrupts is D0 of WR1, and the individual enable bits are in WR15. Individual enable bits
control whether or not a latch is present in the path from the source of the interrupt to the corre-
sponding status bit in RR0. If the individual enable is set to 0, then RR0 reflects the current
unlatched status, and if the individual enable is set to 1, then RR0 reflects the latched status.
The latches for the external/status interrupts are not independent. Rather, they all close at the same
time as a result of a state change in one of the sources of enabled external/status interrupts. This is
displayed schematically in Figure on page 57.
The External/Status IP is set by the closing of the latches and remains set as long as they are
closed. In order to determine which condition(s) require service when an external/status interrupt
is received, the processor should keep an image of RR0 in memory and update this image each
time it executes the external/status service routine.
Thus, a read of RR0 returns the current status for any bits whose individual enable is 0, and either
the current state or the latched state of the remainder of the bits. To guarantee the current status,
the processor should issue a Reset External/Status interrupts command in WR0 to open the
latches. The External/Status IP is set by the closing of the latches and remains set as long as they