Zilog Z80230 - Manual (Page 234)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
227
SCC Interrupt Status Diagram
The SCC uses /INTACK (Interrupt Acknowledge) for recognition of an interrupt acknowledge
cycle. This pin, used with /RD, allows the SCC to gate its interrupt vector onto the data bus. An
active /RD signal during an interrupt acknowledge cycle performs two functions. First, it allows
the highest priority device requesting an interrupt to place its vector on the data bus. Secondly, it
sets the IUS bit in the highest priority device to show the device is now under service.
Input/Output Cycles
Although the SCC is a universal design, certain timing parameters differ from the Z180 timing.
The following subsections discuss the I/O interface for the Z180 MPU and SCC.
Z180 MPU to SCC Interface
Table lists key parameters of the 10 MHz SCC for I/O read/write cycles.
10 MHz SCC Timing Parameters for I/O Read/Write Cycle (Worst Case)
No Symbol Parameter Min Max Units
6 TsA(WR) Address to /WR Low Setup 50 ns
7 ThA(WR) Address to /WR High Hold 0 ns
8 TsA(RD) Address to /RD Low Setup 50 ns
9 ThA(RD) Address to /RD High Hold 0 ns
16 TsCEI(WR) /CE Low to /WR Low Setup 0 ns
17 ThCE(WR) /CE to /WR High Hold 0 ns
19 TsCEI(RD) /CE Low to /RD Low Setup 0 ns