Zilog Z80230 - Manual (Page 219)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
212
Table on page 212 lists the Z180’s basic timing elements for the opcode’s fetch/memory read/
write cycle.
Z180 Opcode Fetch Cycle Timing (One Wait State)
Z8018010 Timing Parameters for Opcode Fetch Cycle
(Worst Case: Z180 10 MHz)
No Symbol Parameter Min Max Units
1 tcyc Clock Cycle Period 100 ns
2 tCHW Clock Cycle High Width 40 ns
3 tCLW Clock Cycle Low Width 40 ns
4 tcf Clock Fall Time 10 ns
6 tAD Clock High to Address
Valid
70 ns
8 tMED1 Clock Low to /MREQ
Low
50 ns
9 tRDD1 Clock Low to /RD Low 50 ns
11 tAH Address Hold Time 10 ns
12 tMED2 Clock Low to /MREQ
High
50 ns