Zilog Z80230 - Manual (Page 141)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
134
mode, and then WR10 to select the CRC preset value and program the Mark/Flag idle bit. The
Loop Mode and Go-Active-On-Poll bits in WR10 should not be set to 1 yet. The flag is written in
WR7 and the various options are selected in WR3 and WR5. At this point, the other registers are
initialized as necessary ( Table ).
The Loop Mode bit (D1) in WR10 is set to 1. When all of this is complete, the transmitter is
enabled by setting bit D3 of WR5 to 1. Now that the transmitter is enabled, the CRC generator is
initialized by issuing the Reset Tx CRC Generator command in WR0. The receiver is enabled by
setting the Go-Active-On-Poll bit (D4) in WR10 to 1. The SCC goes on the loop when seven con-
secutive 1s are received, and signals this by setting the On-Loop bit in RR10. Note that the seven
consecutive 1s will set the Break/Abort and Hunt bits in RR0 also. Once the SCC is on the loop,
the Go-Active-On-Poll bit should be set to 0 until a message is to be transmitted on the loop. To
transmit a message on the loop, the Go-Active-On-Poll bit should be set to 1. At this point, the
SDLC Loop Mode Initialization
Bit Number
Reg D7 D6 D5 D4 D3 D2 D1 D0 Description
WR4 0 0 1 0 0 0 0 0 Select x1 clock, SDLC mode, enable sync
mode
WR3 r x 0 1 1 1 0 0 rx=# of Rx bits/char, No auto enable, enter
Hunt, Enable Rx CRC, Address Search,
No sync character load inhibit
WR5 d t x 0 0 0 r 1 d=inverse of DTR pin, tx=# of Tx bits/char,
use SDLC CRC, r=inverse state of /RTS
pin, CRC enable
WR7 0 1 1 1 1 1 1 0 SDLC Flag
WR6 x x x x x x x x Receiver secondary address
WR15 x x x x x x x 1 Enable access to new register
WR7' 0 1 1 d 1 r 1 1 Enable extended read, Tx INT on FIFO
empty, d=REQUEST timing mode, Rx INT
on 4 char, r=RTS deactivation, auto EOM
reset, auto flag tx
WR10 c d e 1 i 0 1 0 Enable Loop Mode, Go Active On Poll,
c=CRC preset, de=data encoding method,
i=idle line
WR3 r x 0 1 1 1 0 1 Enable Receiver
WR5 d t x 0 1 0 r 1 Enable Transmitter
WR0 1 0 0 0 0 0 0 0 Reset CRC generator