Zilog Z80230 - Manual (Page 224)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
217
Connect the signal Address ANDed together with inactive /IORQ to the /E input. Connect /RD to
/OE of EPROM and SRAM, and /WR to /WE pin of SRAM (Figure on page 218).
Using the second method, there could be a narrow glitch on the signal to the /E-pin during I/O
cycles and the Interrupt acknowledge cycle. During I/O cycles, /IORQ and /RD or /WR go active
at almost the same time. Since the delay times of these signals are similar there is no “overlapping
time” between /CE generated by the address (/IORQ inactive), and /WR or /RD active. During the
Interrupt Acknowledge cycle, /WR and /RD signals are inactive.
To keep the design simple and flexible, use the second method (Figure on page 218). To expand
memory, decode the address A15 NANDed with /USRRAM//USRROM and /IORQ to produce /
CSRAM or /CSROM. These are chip select inputs to chips 55257 or 27C256, respectively. This
either disables or enables on-board ROM or RAM depending upon selection control.
The circuit on Figure on page 218 gives the physical memory address as displayed in Figure on
page 218.
If there are no Z80
® peripherals and /M1 is enabled (M1E bit in Z180 OMCR register set to 1),
active wait states occur only during opcode fetch cycles (Figure on page 219). If the M1E bit is
cleared to 0, /M1E is active only during the Interrupt Acknowledge cycle and Return from Inter-
rupt cycle. This case depends on the propagation delay of the address decoder which uses 135 ns
or faster EPROM assess time (assume there is 20 ns propagation delay). Figure on page 219 dis-
plays the example of this implementation. (Extends Opcode Fetch Cycle Only; Not Working in Z
Mode of Operation)
Memory Interface Logic