Measurement Computing TempScan/1100 - Manual (Page 241)

TempScan / MultiScan User’s Manual 889897 API Command Reference A-45
N
- Set Event Mask
TYPE System
EXECUTION Deferred
SYNTAX Nmask Directly sets the Event Status Enable Register ( ESE ) where mask is in the
form of the number nnn such that 000 < nnn < 255 is summed from the
following conditions:
128 – ESB on Power On 004 – ESB on Query Error
064 – ESB on Buffer 75% Full 002 – ESB on Stop Event
032 – ESB on Command Error 001 – ESB on Acquisition complete
016 – ESB on Execution Error 000 – ESB on Clear Event Mask
008 – ESB on Device Dependent Error
N? Query the Event mask.
DESCRIPTION
The Set Event Mask (
N ) command directly sets the Event Status Enable Register ( ESE ) which in turn, determines
which Event Status Register ( ESR ) conditions are enabled to generate the Event Status Register Bit ( ESR Bit 5 or
ESB ) in the Status Byte Register ( STB ). The bits in the ESE represent an exact image of the bits in the ESR .
When a condition is set in the ESR , its image bit is checked in the ESE . If any image bits are enabled, the bits in
the ESR will be mapped into the ESR Bit 5 (or ESB ) in the STB .
Multiple conditions can be enabled simultaneously. If multiple conditions are contained within the same command
string, each Set Event Mask (
N ) command should be followed by the Execute ( X ) command. Otherwise, since the
resulting Event Mask register value is the logical ORed value, or sum, of the individual values sent, the entire
summed value of all the desired conditions may be sent within one Set Event Mask (
N ) command. The
programmed Event Mask remains enabled until it is cleared by the receipt of a N000 command, or the receipt of
a Reset Power-On ( *R ) command.
The following list outlines the possible conditions of the Event Status Enable Register ( ESE ), as reflected in the
Event Status Register ( ESR ):
•
N128 : ESB on Power On ( ESE Bit 7). Sending this command will allow the setting of the ESB when the
unit is first powered up or when the Reset Power-On ( *R ) command is issued.
• N064 : ESB on Buffer 75% Full ( ESE Bit 6). Sending this command will allow the setting of the ESB when
the Acquisition Buffer has been filled to at least 75% of its capacity.
• N032 : ESB on Command Error ( ESE Bit 5). Sending this command will allow the setting of the ESB when
an illegal command or command syntax error is detected.
•
N016 : ESB on Execution Error ( ESE Bit 4). Sending this command will allow the setting of the ESB when
one of several errors has occurred during the execution of a command.
• N008 : ESB on Device Dependent Error ( ESE Bit 3). Sending this command will allow the setting of the
ESB when a conflict error has occurred. A conflict error is generated when a command cannot execute
correctly because it would interfere with other commands or settings.
• N004 : ESB on Query Error ( ESE Bit 2). Sending this command will allow the setting of the ESB when the
controller has attempted to read from the output queue when no response is present or pending, or when a
response has been lost. Data may be lost when too much data is requested to be buffered in the queue,
where the controller has sent a new query before reading the response to a prior query.
• N002 : ESB on Stop Event ( ESE Bit 1). Sending this command will allow the setting of the ESB when the
user-defined Stop (trigger stop event) of a configured acquisition has been satisfied.
•
N001 : ESB on Acquisition Complete ( ESE Bit 0). Sending this command will allow the setting of the ESB
when the acquisition operation has been completed.
• N000 : This is the power-on default mask value. Sending this command clears the entire mask of the Event
Status Enable ( ESE ) Register to zero.
For more information, see section Status-Reporting & Mask Registers in the chapter System Operation.
EXAMPLE
PRINT#1, “OUTPUT07;N0X” ‘ Clear the Event Status Enable Register ( ESE )
PRINT#1, “OUTPUT07;N3X” ‘ Enable ESB on detection of Stop Event or Acquisition Complete
( 003 = 002 + 001 )