Measurement Computing TempScan/1100 - Manual (Page 113)

TempScan / MultiScan User's Manual 889897 System Operation 5-23
The TempScan/1100 or MultiScan/1200 sets the Message Available Bit (
MAV
,Bit 4) in the Status Byte
Register (
STB
) to determine if data can be read by the controller. This is the only status register which may
require the RS-232/RS-422 serial interface to implement a different read command – Query the Status Byte
Register (
U1
) – than the IEEE 488 interface which primarily implements the Serial Poll (
SPOLL
) command
(but can also use the
U1
command).
The Status Byte Register (
STB
) indicates which critical operation events, if any, have occurred. Its bits and
the events that set them, are as follows:
• Buffer Overrun (Bit 7): Set if an overrun of the Acquisition Buffer occurs. It is cleared when the
buffer becomes empty by either reading out the contents of the buffer or performing the Flush
Acquisition Buffer (
*B
) command.
• Request for Service Bit (RQS) or Master Summary Status Bit (MSS) (Bit 6): Set when the
TempScan/1100 or MultiScan/1200 unit is requesting service. It is cleared when the following is
performed: Serial Poll (
SPOLL
) command (IEEE 488 only) or the following User Status (
U
) command
– Query the Status Byte Register (
U1
) (IEEE 488 or RS-232/RS-422 serial).
• Event Status Register Bit (ESB) (Bit 5): Reflects the logical OR of all the bits in the Event Status
Register (
ESR
) ANDed with their equivalent enable bits in the Event Status Enable Register (
ESE
). This
bit is set if at least one bit in the
ESR
is set and its corresponding bit in the
ESE
is also set.
• Message Available (MAV) (Bit 4): Set when there is data available in the output queue to be read. It
is cleared when the output queue is empty. This bit reflects whether any command responses are still in
the output queue.
• Scan Available (Bit 3): Set when at least one acquisition scan is available in the Acquisition Buffer to
be read. This bit is cleared when there are no scans available in the buffer to be read.
• Ready (Bit 2): Set when the TempScan/1100 or MultiScan/1200 unit has completed executing a set of
commands and is ready to process another command from the IEEE 488 bus controller. It is cleared
when the unit is processing a command line. This bit should be examined with a Serial Poll (
SPOLL
)
prior to issuing a new command line. This allows any detected errors to be traced to the specific
command line containing the error. If all of the setup information for a specific operation is included in
one line, this bit also indicates when all processing is done and the Execute (
X
) command is completed.
This ensures that the unit is finished processing all of its internal state changes before initiating any
further activity.
• Triggered (Bit 1): Set when the TempScan/1100 or MultiScan/1200 unit has detected a valid Trigger
(trigger start event) or Stop (trigger stop event) condition from the programmed trigger source. This bit
is cleared when the acquisition is complete or the Trigger or Stop is reconfigured.
• Alarm (Bit 0): Set when the TempScan/1100 or MultiScan/1200 unit has detected a valid alarm
condition. This bit is cleared whenever the alarm condition no longer exists.
For more information, see command User Status ( U ) in the chapter API Command Reference.
Mask Registers
Event Status Enable Register (ESE)
The Event Status Enable Register (
ESE
) is a Read/Write/Clear register in that they can be written and
cleared, as well as read by the controller, via the following Set Event Mask (
N
) commands –
N?
,
Nmask
,
and
N0
, respectively.
The Event Status Enable Register (
ESE
) may be used to define which bits in the Event Status Register (
ESR
)
will be mapped into the
ESR
Bit 5 (or
ESB
) in the Status Byte Register (
STB
). The bits in the
ESE
represent
an exact image of the bits in the
ESR
. When a condition is set in the
ESR
, its image bit is checked in the
ESE
. If any image bits are enabled, the bits in the
ESR
will be mapped into the
ESR
Bit 5 (or
ESB
) in the
STB
.