Measurement Computing TempScan/1100 - Manual (Page 112)

5-22 System Operation 889897 TempScan / MultiScan User's Manual
• Channel Configuration Error (Bit 2): Set when a channel has been inappropriately configured, either
because the channel is not present or because the specified channel type is incompatible with the
scanning card type installed. This bit is one of the
ESC
Bits 2 to 7, which together maps to the
Execution Error Bit (Bit 4) in the
ESR
.
• Invalid Device Dependent Command Option (IDDCO) (Bit 1): Set when a command parameter is out
of range or missing. This bit in turn maps to the Device Dependent Error Bit (Bit 3) in the
ESR
.
• Invalid Device Dependent Command (IDDC) (Bit 0): Set when there is a command syntax error.
This bit in turn maps to the Command Error Bit (Bit 5) in the
ESR
.
For more information, see command Query Error Status (
E?
) in the chapter API Command Reference.
Event Status Register (ESR)
The Event Status Register (
ESR
) is a Read/Clear-Only register in that it may only be read and cleared by the
controller, via the following User Status (
U
) command – Query and clear the Event Status Register (
U0
). .
The read operation is a destructive read since it clears the register as it is read. This register can only be
written to by internal TempScan/1100 or MultiScan/1200 operations.
The Event Status Register (
ESR
) indicates which special events, if any, have occurred. Its bits and the
events that set them, are as follows:
• Power On (Bit 7): Set when the TempScan/1100 or MultiScan/1200 unit is first powered up or when
the Reset Power-On (
*R
) command is issued.
• Buffer 75% Full (Bit 6): Set when the Acquisition Buffer has been filled to at least 75% of its
capacity. This bit is cleared when the amount of data in the Acquisition Buffer falls below 75% of its
capacity.
• Command Error (Bit 5): Set when an illegal command or command syntax error is detected. The
Invalid Device Dependent Command (IDDC) Bit (Bit 0) in the Error Source Register (
ESC
) maps to
this bit.
• Execution Error (Bit 4): Set when one of several errors has occurred during the execution of a
command. Bits 2 through 7 in the Error Source Register (
ESC
) together map to this bit.
• Device Dependent Error (Bit 3): Set when a conflict error has occurred. A conflict error is generated
when a command cannot execute correctly because it would interfere with other commands or settings.
The Invalid Device Dependent Command Option (IDDCO) Bit (Bit 1) in the Error Source Register
(
ESC
) maps to this bit.
• Query Error (Bit 2): Set when the controller has attempted to read from the TempScan/1100 or
MultiScan/1200 output queue when no response is present or pending, or when a response has been
lost. Data may be lost when too much data is requested to be buffered in the queue, where the
controller has sent a new query before reading the response to a prior query.
• Stop Event (Bit 1): Set when the user-defined Stop (trigger stop event) of a configured acquisition has
been satisfied. This bit is cleared when a new acquisition is configured either through the Set Trigger
Configuration (
T
) command or when the unit is re-armed via the Auto Re-arm mode.
• Acquisition Complete (Bit 0): Set when the acquisition operation has been completed. An acquisition
is complete when the TempScan/1100 or MultiScan/1200 unit has finished the current acquisition. The
bit will be cleared when a new acquisition is configured through the Set Trigger Configuration (
T
)
command.
For more information, see command User Status (
U
) in the chapter API Command Reference.
Status Byte Register (STB)
The Status Byte Register (
STB
) is a Read-Only register in that it can only be read by the controller, via the
Serial Poll (
SPOLL
) command (IEEE 488 only) or the following User Status (
U
) command – Query the
Status Byte Register (
U1
) (IEEE 488 or serial). This register can only be cleared or written to by the
internal processes of the TempScan/1100 or MultiScan/1200.
The Status Byte Register (
STB
) is at the lowest-level status-reporting register in the register hierarchy.
When the controller accesses this register in real-time via an IEEE 488
SPOLL
command, this access allows
the quick response of certain critical operational status conditions contained in the
STB
. Since this is the
lowest-level register, every other status register in the system, either directly or indirectly, has access to the
STB
via the Event Status Register Bit (
ESR
Bit 5, or
ESB
) in the
STB
. Such access gives these other status
registers the ability to quickly report their general status to the controller.