Brocade FastIron Ethernet Switch Platform and Layer 2 Switching Configuration Guide - Manual (Page 49)

Dynamic buffer allocation for FCX and ICX devices
By default, the traditional stack architecture allocates fixed buffers on a per-priority queue, per-packet
processor basis. The buffers control the total number of packets that can be queued in the outbound
transmit for the port. In instances of heavy traffic bursts to aggregation links, such as in stacking
configurations or mixed-speed environments, momentary oversubscription of the buffers and
descriptors may occur. A descriptor points to one or more packet buffers.
Brocade FastIron stackable devices provide the capability to allocate additional egress buffering and
descriptors to handle momentary bursty traffic periods, especially when other priority queues may not
be in use, or may not be experiencing heavy traffic. This allows users to allocate and fine-tune the depth
of priority buffer queues for each packet processor.
Configuring buffer profiles
There are two different methods of allocating buffers and descriptors to the ports and its queues.
One method uses the qd-descriptor and qd-buffer CLI commands to allocate descriptors and buffers,
respectively, to the port and its queues. This method is available on FCX and ICX devices.
The other method uses user-configurable buffer profiles. This method allows you to define a template of
buffer allocations to be used on a per-port per-queue basis on the devices. When applied, this buffer
profile acts as if you created a series of the qd commands. This buffer profile is a simpler form of
allocating descriptors and buffers to the port and its queues. This method is available on FCX and ICX
devices.
Configuring buffer profiles with qd-descriptor and qd-buffer commands on FCX and ICX devices
The 48-port Brocade stackable switch has two packet processors. The 24-port Brocade stackable
switch has a single packet processor. For devices in a traditional stack, each stack unit has the
possibility of two packet processors, but the second processor for a 24-port stack unit cannot be
configured. The number of actual available packet processors depends on the type and number of
switches in the stack.
For example, for an 8-unit stack of 48 ports, the packet processor numbering scheme is as follows:
• Stack unit 1 - Packet processors 0 and 1
• Stack unit 2 - Packet processors 2 and 3
• Stack unit 3 - Packet processors 4 and 5
• Stack unit 4 - Packet processors 6 and 7
• Stack unit 5 - Packet processors 8 and 9
• Stack unit 6 - Packet processors 10 and 11
• Stack unit 7 - Packet processors 12 and 13
• Stack unit 8 - Packet processors 14 and 15
In this configuration, if stack unit 3 and stack unit 7 are 24-port devices, the odd-numbered packet
processors 5 and 13 cannot be configured, and do not exist, although they are reserved.
Configuration steps for buffer profile with qd-descriptor and qd-buffer commands on
FCX and ICX
The descriptor and buffer allocation process occurs in four sequential steps using the qd-buffer and
qd-descriptor commands.
Dynamic buffer allocation for FCX and ICX devices
FastIron Ethernet Switch Platform and Layer 2 Switching Configuration Guide 49
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