Motorola DSP56012 - Manual (Page 92)

4-12 DSP56012 User’s Manual MOTOROLA
Parallel Host Interface
Host Interface (HI)
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4.4.3 HI—DSP Viewpoint
The DSP views the HI as a memory-mapped peripheral occupying three 24-bit words
in data memory space. The DSP accesses the HI using either standard polled or
interrupt programming techniques. Separate transmit and receive data registers are
double-buffered to allow the DSP and host processor to transfer data efficiently at
high speed. Memory mapping allows communication with the HI registers to use
Figure 4-7 HI Block Diagram
DSP CPU Global
Data Bus
X:$FFE8
X:$FFE9
X:$FFEB
X:$FFEB
24
Receive Byte
Registers
Transmit Byte
Registers
Interrupt Control
Register
(Read/Write)
$0
ICR
$1
CVR
HCR
HSR
$2
ISR
$3
IVR
Control
Logic
HOTX
HORX
$5
RXH
$6
RXM
$7
RXL
$5
TXH
$6
TXM
$7
TXL
Host Control Register
(Read/Write)
Host Status Register
(Read Only)
Host Transmit
Data Register
(Write Only)
Host Recieve
Data Register
(Read Only)
Command Vector
Register
(Read/Write)
Interrupt Vector
Register
(Read/write)
24
24
8
Host MPU
Data Bus
H[7:0]
(Read Only)
(Write Only)
Interrupt Status
Register
(Read Only)
AA0313k