Motorola DSP56012 - Manual (Page 107)

Parallel Host Interface
Host Interface (HI)
MOTOROLA DSP56012 User’s Manual 4-27
When both HM1 and HM0 are cleared, the DMA mode is disabled, and the TREQ
and RREQ control bits are used for host processor interrupt control via the external
HOREQ output pin. Also, in the non-DMA mode, the HACK input pin is used for the
MC68000-family vectored interrupt acknowledge input.
When HM1 or HM0 are set, the DMA mode is enabled, and the HOREQ pin is used
to request DMA transfers. When the DMA mode is enabled, the TREQ and RREQ bits
select the direction of DMA transfers. The HACK input pin is used as a DMA transfer
acknowledge input. If the DMA direction is from DSP to host, the contents of the
selected register are enabled onto the host data bus when HACK is asserted. If the
DMA direction is from host to DSP, the selected register is written from the host data
bus when HACK is asserted.
The size of the DMA word to be transferred is determined by the DMA control bits,
HM0 and HM1. The HI register selected during a DMA transfer is determined by a
2-bit address counter, which is preloaded with the value in HM1 and HM0. The
address counter substitutes for the HOA1 and HOA0 bits of the host during a DMA
transfer. The HI Address bit (HOA2) is forced to 1 during each DMA transfer. The
address counter can be initialized with the INIT bit feature. After each DMA transfer
on the host data bus, the address counter is incremented to the next register. When
the address counter reaches the highest register (RXL or TXL), the address counter is
not incremented, but is loaded with the value in HM1 and HM0. This allows 8-, 16- or
24-bit data to be transferred in a circular fashion and eliminates the need for the
DMA controller to supply the HOA2, HOA1, and HOA0 pins. For 16- or 24-bit data
transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively,
from the host request rate—that is, for every two or three host processor data
transfers of one byte each, there is only one 24-bit DSP CPU interrupt.
Note: Hardware reset, software reset, individual reset, and Stop mode clear HM1
and HM0.
4.4.5.3.7 ICR Initialize Bit (INIT)—Bit 7
The Initialize (INIT) bit is used by the host processor to force initialization of the HI
hardware. Initialization consists of configuring the HI transmit and receive control
bits, and loading HM1 and HM0 into the internal DMA address counter. Loading
HM1 and HM0 into the DMA address counter causes the HI to begin transferring
data on a word boundary rather than transferring only part of the first data word.
4.4.5.4 HI Initialization
There are two methods of initialization:
1. allowing the DMA address counter to be automatically set after transferring a
word, and
2. setting the INIT bit, which sets the DMA address counter.