Motorola DSP56012 - Manual (Page 157)

Serial Host Interface
Serial Host Interface Programming Model
MOTOROLA DSP56012 User’s Manual 5-9
5.4.3 SHI Host Receive Data FIFO (HRX)—DSP Side
The 24-bit Host Receive data FIFO (HRX) is a 10-word deep, First-In-First-Out (FIFO)
register used for Host-to-DSP data transfers. The serial data is received via the shift
register and then loaded into the HRX. In the single-byte data transfer mode, the
most significant byte of the shift register is transferred to the HRX (the other bits are
filled with 0s); in the double-byte mode the two most significant bytes are transferred
(the least significant byte is filled with 0s), and in the triple-byte mode, all 24 bits are
transferred to the HRX. The HRX may be read by the DSP while the FIFO is being
loaded from the shift register. The HRX is reset to the empty state (cleared) when the
chip is in Stop mode, and during hardware reset, software reset, and individual reset.
5.4.4 SHI Slave Address Register (HSAR)—DSP Side
The 24-bit Slave Address Register (HSAR) is used when the SHI operates in the I
2
C
Slave mode and is ignored in the other operational modes. HSAR holds five bits of
the 7-bit slave address of the device. The SHI also acknowledges the general call
address (all 0s, 7-bit address, and a 0 R/W bit) specified by the I
2
C protocol. HSAR
cannot be accessed by the host processor.
5.4.4.1 HSAR Reserved Bits—Bits 17–0,19
These bits are reserved and unused. They read as 0s and should be written with 0s
for future compatibility.
5.4.4.2 HSAR I
2
C Slave Address (HA[6:3], HA1)—Bits 23–20,18
Part of the I
2
C slave device address is stored in the read/write HA[6:3], HA1 bits of
HSAR. The full 7-bit slave device address is formed by combining the HA[6:3], HA1
bits with the HA0 and HA2 pins to obtain the HA[6:0] slave device address. The full
7-bit slave device address is compared to the received address byte whenever an I
2
C
master device initiates an I
2
C bus transfer. During hardware reset or software reset,
HA[6:3] = 1011 while HA1 is cleared; this results in a default slave device address of
1011_HA2_0_HA0.
5.4.5 SHI Clock Control Register (HCKR)—DSP Side
The SHI Clock Control Register (HCKR) is a 24-bit read/write register that controls
the SHI clock generator operation. The HCKR bits should be modified only while the
SHI is in the individual reset state (HEN = 0 in the HCSR).