Motorola DSP56012 - Manual (Page 267)

Motorola I-3
Host Mode Control bits (HM1–HM0) 4-26
host port
usage considerations 2-10
host registers after reset
as seen by host processor 4-33
Host Request bit (HOREQ) 4-32
Host Request pin (PB13/HOREQ) 4-35
Host Status Register (HSR) 4-16
host to DSP DMA procedure 4-62
host to DSP internal processing 4-61
Host Transmit Data Empty bit (HTDE) 4-16
Host Transmit Data register (HOTX) 4-19
HOTX register 4-19
HR/W 4-35
HRDF bit 4-21
HREQ Function In SHI Slave Modes 5-15
HRFF (HCSR Host Receive FIFO Full) 5-18
HRIE0-HRIE1 (HCSR Receive Interrupt
Enable) 5-16
HRNE (HCSR Host Receive FIFO Not Empty) 5-18
HROE (HCSR Host Receive Overrun Error) 5-18
HRQE0-HRQE1 (HCSR Host Request Enable) 5-15
HSR register 4-16
bit 1—Host Transmit Data Empty bit
(HTDE) 4-16
bit 5, 6—reserved 4-18
bit 7—DMA Status bit (DMA) 4-18
HTDE (HCSR Host Transmit Data Empty) 5-17
HTDE bit 4-16 , 4-21
HTIE (HCSR Transmit Interrupt Enable) 5-16
HTUE (HCSR Host Transmit Underrun Error) 5-17
HV 4-29 , 4-53
HV5–HV0 bits 4-29
I
I
2
C 1-18 , 5-3 , 5-20
Bit Transfer 5-20
Bus Protocol For Host Read Cycle 5-22
Bus Protocol For Host Write Cycle 5-22
Data Transfer Formats 5-22
Master Mode 5-27
Protocol for Host Read Cycle 5-22
Protocol for Host Write Cycle 5-22
Receive Data In Master Mode 5-29
Receive Data In Slave Mode 5-26
Slave Mode 5-25
Start and Stop Events 5-21
Transmit Data In Master Mode 5-29
Transmit Data In Slave Mode 5-27
I
2
C Bus Acknowledgment 5-21
I
2
C Mode 5-3
I
2
S Format 1-19
I2S Format 6-3
ICR register 4-24
bit 0—Receive Request Enable bit (RREQ) 4-24
bit 1—Transmit Request Enable bit
(TREQ) 4-24
bit 3—Host Flag 0 bit (HF0) 4-25
bit 4—Host Flag 1 bit (HF1) 4-26
bit 5, 6—Host Mode Control bits
(HM1–HM0) 4-26
bit 7—Initialize bit (INIT) 4-27
reserved bit 4-25
IEC958 8-3
INIT bit 4-27
Initialize bit (INIT) 4-27
Input/Output 1-16
Instruction Set Summary B-8
Inter Integrated Circuit Bus 5-3
Inter Integrated-Circuit Bus 1-18
Internal Exception Priorities
SHI 5-7
Internal Interrupt Priorities
SAI 6-9
internal processing
DSP to host 4-64
host to DSP 4-61
Interrupt
Priority Register (IPR) 3-15
Sources 1-13 , B-5
Starting Addresses 1-13 , B-5
interrupt
DMA 4-41
host command 4-51
host receive data 4-51
host transmit data 4-51
non-DMA 4-39
interrupt and mode control 2-8
interrupt control 2-8
Interrupt Control Register (ICR) 4-24
Interrupt Status Register (ISR) 4-30
Interrupt Vector Register (IVR) 4-32
Interrupt Vectors
SHI 5-7
Interrupts — See Section 3
ISR register
4-30
bit 0—Receive Data Register Full bit
(RXDF) 4-30
bit 1—Transmit Data Register Empty bit
(TXDE) 4-31
bit 2—Transmitter Ready bit (TRDY) 4-31
bit 3—Host Flag 2 bit (HF2) 4-31
bit 4—Host Flag 3 bit (HF3) 4-31
bit 5—reserved 4-31
bit 6—DMA Status bit (DMA) 4-32
bit 7—Host Request bit (HOREQ) 4-32
IVR register 4-32