Motorola DSP56012 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for DSP56012 Motorola
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 270 |
| Size: | 2.20 MB |
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Document Outline
- Overview
- Table11 High True / Low True Signal Conventions
- Table12 DSP56012 Internal Memory Configurations
- Figure11 DSP56012 Block Diagram
- Table13 Interrupt Starting Addresses and Sources (Continued)
- Table14 Internal Memory Configurations
- Table15 On-chip Peripheral Memory Map (Continued)
- Signal Descriptions
- Table21 DSP56012 Functional Signal Groupings
- Figure21 DSP56012 Signals
- Table22 Power Inputs
- Table23 Grounds
- Table24 Phase Lock Loop Signals
- Table25 Interrupt and Mode Control (Continued)
- Table26 Host Interface (Continued)
- Table27 Serial Host Interface (SHI) Signals (Continued)
- Table28 Serial Audio Interface (SAI) Receive Signals
- Table29 Serial Audio Interface (SAI) Transmit Signals
- Table210 General Purpose I/O (GPIO) Signals
- Table211 Digital Audio Interface (DAX) Signals
- Table212 On-Chip Emulation Port (OnCE) Signals (Continued)
- Memory, Operating Modes, and Interrupts
- Table31 Internal Memory Configurations
- Figure31 Memory Maps for PEA = 0, PEB = 0
- Figure32 Memory Maps for PEA = 1, PEB = 0
- Figure33 Memory Maps for PEA = 0, PEB = 1
- Figure34 Memory Maps for PEA = 1, PEB = 1
- Table32 Internal I/O Memory Map (Continued)
- Figure35 Operating Mode Register (OMR)
- Table33 Operating Modes
- Figure36 Interrupt Priority Register (Addr X:$FFFF)
- Table34 Interrupt Priorities (Continued)
- Table35 Interrupt Vectors (Continued)
- Figure37 PLL Configuration
- Parallel Host Interface
- Figure41 Port B Interface
- Figure42 Parallel Port B Registers
- Figure43 Port B GPIO Signals and Registers
- Figure44 Port B I/O Pin Control Logic
- Figure45 Instructions to Write/Read Parallel Data with Port B
- Figure46 I/O Port B Configuration
- Figure47 HI Block Diagram
- Figure48 HI Programming Model–DSP Viewpoint
- Figure49 HI Flag Operation
- Table41 HI Registers after Reset—DSP CPU Side (Continued)
- Figure410 Host Processor Programming Model–Host Side
- Figure411 HI Register Map
- Table42 HOREQ Pin Definition
- Figure412 HSR and HCR Operation
- Table43 HI Mode Bit Definition
- Table44 HOREQ Pin Definition
- Figure413 Command Vector Register
- 4.4.5.5.2 CVR Reserved—Bit 6
- 4.4.5.5.3 CVR Host Command (HC)—Bit 7
- 4.4.5.6 Interrupt Status Register (ISR)
- 4.4.5.6.1 ISR Receive Data Register Full (RXDF)—Bit 0
- 4.4.5.6.2 ISR Transmit Data Register Empty (TXDE)—Bit 1
- 4.4.5.6.3 ISR Transmitter Ready (TRDY)—Bit 2
- 4.4.5.6.4 ISR HI Flag 2 (HF2)—Bit 3 (read only)
- 4.4.5.6.5 ISR HI Flag 3 (HF3)—Bit 4 (read only)
- 4.4.5.6.6 ISR Reserved—Bit 5
- 4.4.5.6.7 ISR DMA Status (DMA)—Bit 6
- 4.4.5.6.8 ISR Host Request (HOREQ)—Bit 7
- 4.4.5.7 Interrupt Vector Register (IVR)
- 4.4.5.8 Receive Byte Registers (RXH, RXM, RXL)
- 4.4.5.9 Transmit Byte Registers (TXH, TXM, TXL)
- 4.4.5.10 Registers After Reset
- Table45 HI Registers after Reset (Host Side)
- Table46 Port B Pin Definitions
- Figure414 Host Processor Transfer Timing
- Figure415 Interrupt Vector Register Read Timing
- Figure416 HI Interrupt Structure
- Figure417 DMA Transfer Logic and Timing
- Figure418 HI Initialization Flowchart
- Figure419 HI Initialization—DSP Side
- Figure420 HI Initialization—Host Side, Interrupt Mode
- Figure421 HI Mode and INIT Bits
- Figure422 HI Initialization—Host Side, Polling Mode
- Figure423 HI Configuration—Host Side
- Figure424 HI Initialization–Host Side, DMA Mode
- Figure425 Bits Used for Host-to-DSP Transfer
- Figure426 Data Transfer from Host to DSP
- Figure427 Host Command
- Figure428 Receive Data from Host—Main Program
- Figure429 Receive Data from Host Interrupt Routine
- Figure430 Transmit/Receive Byte Registers
- Figure431 Bootstrap Using the Host Interface
- Figure432 Bits Used for DSP to Host Transfer
- Figure433 Data Transfer from DSP to Host
- Figure434 Main Program: Transmit 24-bit Data to Host
- Figure435 HI Hardware–DMA Mode
- Figure436 DMA Transfer and HI Interrupts
- Figure437 Host to DSP DMA Procedure
- 4.4.8.3.3 DSP to HI —Internal Processing
- 4.4.8.3.4 DSP to Host—DMA Procedure
- 4.4.8.4 HI Port Usage Considerations—Host Side
- 4.4.8.4.1 Unsynchronized Reading of Receive Byte Registers
- 4.4.8.4.2 Overwriting Transmit Byte Registers
- 4.4.8.4.3 Synchronization of Status Bits from DSP to Host
- 4.4.8.4.4 Overwriting the Host Vector
- 4.4.8.4.5 Cancelling a Pending Host Command interrupt
- 4.4.8.4.6 Coordinating Data Transfers
- 4.4.8.4.7 Unused Pins
- Serial Host Interface
- Figure51 Serial Host Interface Block Diagram
- Figure52 SHI Clock Generator
- Figure53 SHI Programming Model—Host Side
- Figure54 SHI Programming Model—DSP Side
- Table51 SHI Interrupt Vectors
- Table52 SHI Internal Interrupt Priorities
- Figure55 SHI I/O Shift Register (IOSR)
- Figure56 SPI Data-To-Clock Timing Diagram
- Table53 SHI Noise Reduction Filter Mode
- Table54 SHI Data Size
- Table55 HREQ Function In SHI Slave Modes
- Table56 HCSR Receive Interrupt Enable Bits
- 5.4.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 14
- 5.4.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15
- 5.4.6.14 Host Receive FIFO Not Empty (HRNE)—Bit 17
- 5.4.6.15 Host Receive FIFO Full (HRFF)—Bit 19
- 5.4.6.16 Host Receive Overrun Error (HROE)—Bit 20
- 5.4.6.17 Host Bus Error (HBER)—Bit 21
- 5.4.6.18 HCSR Host Busy (HBUSY)—Bit 22
- 5.5 Characteristics Of The SPI Bus
- 5.6 Characteristics Of The I2C Bus
- Figure57 I2C Bit Transfer
- Figure58 I2C Start and Stop Events
- Figure59 Acknowledgment on the I2C Bus
- Figure510 I2C Bus Protocol For Host Write Cycle
- Figure511 I2C Bus Protocol For Host Read Cycle
- Serial Audio Interface
- Figure61 SAI Baud-Rate Generator Block Diagram
- Figure62 SAI Receive Section Block Diagram
- Figure63 SAI Transmit Section Block Diagram
- Figure64 SAI Registers
- Table61 SAI Interrupt Vector Locations
- Table62 SAI Internal Interrupt Priorities
- Table63 Receiver Word Length Control
- Figure65 Receiver Data Shift Direction (RDIR) Programming
- Figure66 Receiver Left/Right Selection (RLRS) Programming
- Figure67 Receiver Clock Polarity (RCKP) Programming
- Figure68 Receiver Relative Timing (RREL) Programming
- Figure69 Receiver Data Word Truncation (RDWT) Programming
- 6.3.2.11 RCS Receiver Interrupt Enable (RXIE)—Bit 11
- 6.3.2.12 RCS Receiver Interrupt Location (RXIL)—Bit 12
- 6.3.2.13 RCS Receiver Left Data Full (RLDF)—Bit 14
- 6.3.2.14 RCS Receiver Right Data Full (RRDF)—Bit 15
- 6.3.3 SAI Receive Data Registers (RX0 and RX1)
- 6.3.4 Transmitter Control/Status Register (TCS)
- Table64 Transmitter Word Length
- Figure610 Transmitter Data Shift Direction (TDIR) Programming
- Figure611 Transmitter Left/Right Selection (TLRS) Programming
- Figure612 Transmitter Clock Polarity (TCKP) Programming
- Figure613 Transmitter Relative Timing (TREL) Programming
- Figure614 Transmitter Data Word Expansion (TDWE) Programming
- 6.3.4.11 TCS Transmitter Interrupt Enable (TXIE)—Bit 11
- 6.3.4.12 TCS Transmitter Interrupt Location (TXIL)—Bit 12
- 6.3.4.13 TCS Reserved Bit—Bit 13
- 6.3.4.14 TCS Transmitter Left Data Empty (TLDE)—Bit 14
- 6.3.4.15 TCS Transmitter Right Data Empty (TRDE)—Bit 15
- 6.3.5 SAI Transmit Data Registers (TX2, TX1 and TX0)
- 6.4 Programming Considerations
- GPIO
- Figure71 GPIO Control/Data Register
- Table71 GPIO Pin Configuration
- Figure72 GPIO Circuit Diagram
- Digital Audio Transmitter
- Figure81 Digital Audio Transmitter (DAX) Block Diagram
- Table81 DAX Interrupt Vectors
- Table82 DAX Interrupt Priority
- Figure82 DAX Programming Mode
- Table83 Clock Source Selection
- 8.5.4.5 XCTR Reserved Bits—Bits 5-9, 16-23
- 8.5.4.6 DAX Channel A Validity (XVA)—Bit 10
- 8.5.4.7 DAX Channel A User Data (XUA)—Bit 11
- 8.5.4.8 DAX Channel A Channel Status (XCA)—Bit 12
- 8.5.4.9 DAX Channel B Validity (XVB)—Bit 13
- 8.5.4.10 DAX Channel B User Data (XUB)—Bit 14
- 8.5.4.11 DAX Channel B Channel Status (XCB)—Bit 15
- 8.5.5 DAX Status Register (XSTR)
- Figure83 DAX Relative Timing
- Table84 Preamble Bit Patterns
- Figure84 Preamble sequence
- Figure85 Clock Multiplexer Diagram
- Bootstrap ROM Contents
- Programming Reference