Motorola DSP56012 - Manual (Page 36)

1-16 DSP56012 User’s Manual MOTOROLA
Overview
DSP56012 Architectural Overview
1.3.3.5 Memory Configuration Bits
Through the use of bits PEA and PEB in the Operating Mode Register (OMR), four
different memory configurations are possible, to provide appropriate memory sizes
for a variety of applications (see
Table 1-4 ).
1.3.3.6 External Memory
The DSP56012 does not extend internal memory off chip.
1.3.3.7 Bootstrap ROM
The bootstrap ROM occupies locations 0–31 ($0–$1F) in the memory map on the
DSP56012. The bootstrap ROM is factory- programmed to perform the bootstrap
operation following hardware reset. It downloads a 256-word user program from
either the HI port or the SHI port (in SPI or I
2
C format). The bootstrap ROM activity
is controlled by the bits MC, MB, and MA, which are located in the OMR. When in
the Bootstrap mode, the first 256 words of program RAM are read-disabled but
write-accessible. The contents of the bootstrap ROM are listed in
Appendix A .
1.3.3.8 Reserved Memory Spaces
The memory spaces marked as reserved should not be accessed by the user. They are
reserved for the expansion of future versions or variants of this DSP. Write
operations to the reserved range are ignored. Read operations from addresses in the
reserved range (with values greater than or equal to $2E00 in X memory space and
$2800 in Y memory space, and values from the reserved area of program memory
space), return the value $000005, which is the opcode for the ILLEGAL instruction,
and causes an illegal instruction interrupt service. If a read access is performed from
the reserved area below address $2000 in X or Y data memory, the resulting data will
be undetermined. If an instruction fetch is attempted from addresses in the reserved
area, the value returned is $000005 (ILLEGAL opcode).
1.3.4 Input/Output
A variety of system configurations are facilitated by the DSP56012 Input/Output
(I/O) structure. Each I/O interface has its own control, status, and double-buffered
data registers that are memory-mapped in the X-data memory space (see
Table 1-5 ).
The HI, SHI, SAI , and DAX also have several dedicated interrupt vector addresses
and control bits to enable and disable interrupts (see
Table 1-3 on page 1-13). These
interrupt vectors minimize the overhead associated with servicing an interrupt by
immediately executing the appropriate service routine. Each interrupt can be
configured to one of three maskable priority levels.