Motorola DSP56012 - Manual (Page 28)

1-8 DSP56012 User’s Manual MOTOROLA
Overview
DSP56012 Architectural Overview
• Two sets of SAI interrupt vectors
– SHI features:
• Single master capability
• SPI and I
2
C protocols
• 10-word receive FIFO
• Support for 8-, 16- and 24-bit words.
– Byte-wide Parallel Host Interface with DMA support capable of
reconfiguration as fifteen General Purpose Input/Output (GPIO) lines
– DAX features one serial transmitter capable of supporting S/PDIF, IEC958,
CP-340, and AES/EBU formats.
– Eight dedicated, independent, programmable GPIO lines
– On-chip peripheral registers memory mapped in data memory space
– OnCE™ port for unobtrusive, processor speed-independent debugging
– Software programmable PLL-based frequency synthesizer for the core
clock
– Power saving Wait and Stop modes
– Fully static, HCMOS design for operating frequencies from 81 MHz down
to DC
– 100-pin plastic Thin Quad Flat Pack (TQFP) surface-mount package
– 5 V power supply
1.3 DSP56012 ARCHITECTURAL OVERVIEW
The DSP56012 is a member of the 24-bit DSP56000 family. The DSP is composed of
the 24-bit DSP56000 core, memory, and a set of peripheral modules, as shown in
Figure 1-1 . The 24-bit DSP56000 core is composed of a Data Arithmetic Logic Unit
(ALU), an Address Generation Unit (AGU), a Program Controller, an On-Chip
Emulation (OnCE
)
port, and a PLL designed to allow the DSP to run at full speed
while using a low-speed clock. The DSP56000-family architecture, upon which the
DSP56012 is built, was designed to maximize throughput in data-intensive digital
signal processing applications. The result is a dual-natured, expandable architecture
with sophisticated on-chip peripherals and versatile GPIO.