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3 host to dsp—bootstrap loading using the hi, Figure430 transmit/receive byte registers, Host to dsp—bootstrap loading using the hi -54 – Motorola DSP56012 User Manual

Page 134: Figure 4-30, Transmit/receive byte registers -54, Parallel host interface host interface (hi)

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4-54

DSP56012 User’s Manual

MOTOROLA

Parallel Host Interface

Host Interface (HI)

4.4.8.2.3

Host to DSP—Bootstrap Loading Using the HI

The circuit shown in

Figure 4-31

will cause the DSP to boot through the HI on power

up. During the bootstrap program, the DSP looks at the MODC, MODB, and MODA
bits. If the MODC:MODB:MODA bits = 001, the DSP will load from the HI. Data is
written by the host processor in a pattern of four bytes, with the high byte being a
dummy and the low byte being the low byte of the DSP word (see

Figure 4-31

and

Figure 4-30

).

Figure 4-32

on page 4-57 shows how an 8-, 16-, 24-, or 32-bit word in

the host processor maps into the HI registers. The HI register at address $4 is not
used and will read as 0. It is not necessary to use address $4, but since many host
processors are 16- or 32-bit processors, address $4 will often be used as part of the 16-
or 32-bit word. The low order byte (at $7) should always be written last, since writing
to it causes the HI to initiate the transfer of the word to the HORX. Data is then
transferred from the HORX to the DSP program memory. If the host processor needs
to terminate the bootstrap loading before 512 words have been downloaded, it can
set the HF0 bit in the ICR. The DSP will then terminate the download and start
executing at location P:$0000. Since the DSP56012 is typically faster than the host
processor, handshaking during the data transfer is normally not required.

Figure 4-30 Transmit/Receive Byte Registers

Host
Data

Read—00000000

Write—XXXXXXXX

Host

Transmit/Receive

Byte Registers

Host Byte

Address

0 0 0 0 0 0 0 0

TXH/RXH
High Byte

TXM/RXM

Middle Byte

TXL/RXL
Low Byte

8-bit Transfer

16-bit Transfer

24-bit Transfer

32-bit Transfer, Lowest 24 Bits Are Significant

Access to

Low Byte

Initiates

Transfer

NOTE: Access the low byte last

7

0

4

5

6

7

31

High

Middle

Low

24 23

16 15

8

7

0

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