Motorola DSP56012 - Manual (Page 32)

1-12 DSP56012 User’s Manual MOTOROLA
Overview
DSP56012 Architectural Overview
AGU registers may be read from or written to via the Global Data Bus as 16-bit
operands. The AGU has two modulo arithmetic units that can generate two
independent 16-bit addresses every instruction cycle for any two of the XAB, YAB, or
PAB.
1.3.2.3 Program Control Unit
The program control unit performs instruction prefetch, instruction decoding,
hardware DO loop control, and exception processing. It contains six directly
addressable registers—the Program Counter (PC), Loop Address (LA), Loop Counter
(LC), Status Register (SR), Operating Mode Register (OMR), and Stack Pointer (SP).
The program control unit also contains a 15 level by 32-bit system stack memory. The
16-bit PC can address 65,536 (64 K) locations in program memory space.
1.3.2.4 Data Buses
Data movement on the chip occurs over four bidirectional 24-bit buses—the X Data
Bus (XDB), the Y Data Bus (YDB), the Program Data Bus (PDB), and the Global Data
Bus (GDB). Certain instructions concatenate XDB and YDB to form a 48-bit data bus.
Data transfers between the Data ALU and the two data memories, X and Y, occur
over the XDB and YDB, respectively. These transfers can occur simultaneously on the
DSP, maximizing data throughput. All other data transfers, such as I/O transfers to
internal peripherals, occur over the GDB. Instruction word pre-fetches take place
over the PDB in parallel with data transfers. Transfers between buses are
accomplished through the internal bus switch.
1.3.2.5 Address Buses
Addresses are specified for internal X data memory and Y data memory using two
unidirectional 16-bit buses—the X Address Bus (XAB) and the Y Address Bus (YAB).
program memory addresses are specified using the 16-bit Program Address Bus
(PAB).
1.3.2.6 Phase Lock Loop (PLL)
The Phase Lock Loop (PLL) reduces the need for multiple oscillators in a system
design, thus reducing the overall system cost. An additional benefit of the PLL is that
it permits the use of a low-frequency external clock with no sacrifice of processing
speed. The PLL converts the low-frequency external clock to the high speed internal
clock needed to run the DSP at maximum speed. This diminishes the electromagnetic
interference generated by high frequency clocking. The PLL performs frequency
multiplication to allow the processor to use almost any available external system
clock for full-speed operation. It also improves the synchronous timing of the
processor’s external memory port, significantly reducing the timing skew between
EXTAL and the internal chip phases when the Multiplication Factor (MF)
≤
4. The
PLL is unique in that it provides a low power divider on its output, which can reduce
or restore the chip operating frequency without losing the PLL lock.