Motorola DSP56012 - Manual (Page 266)

I-2 Motorola
Circuit Diagram 7-5
Control/Data Register 7-3
GPIOR
Control Bits 7-4
Data Bits 7-4
Data Direction Bits 7-4
Pin Definition 7-4
Programming Model 7-3
programming port B 4-8
Ground 2-6
PLL 2-6
H
H0–H7 pins 4-35
HA1, HA3-HA6 (HSAR I
2
C Slave Address) 5-9
HACK pin 4-36
HBER (HCSR Bus Error) 5-18
HBIE (HCSR Bus Error Interrupt Enable) 5-16
HBUSY (HCSR Host Busy) 5-19
HC bit 4-30
HCKR (SHI Clock Control Register) 5-9
HCP bit 4-21
HCR register
bit 5–7—reserved 4-16
HCSR
Receive Interrupt Enable Bits 5-17
SHI Control/Status Register 5-13
HDM0-HDM5 (HCKR Divider Modulus
Select) 5-12
HEN 4-35
HEN (HCSR SHI Enable) 5-13
HF0 bit 4-21 , 4-25
reading during transition 4-21
HF1 bit 4-21 , 4-26
reading during transition 4-21
HF2 bit 4-31
HF3 bit 4-31
HFIFO (HCSR FIFO Enable Control) 5-14
HFM0-HFM1 (HCKR Filter Mode) 5-12
HI
application examples
bootstrap from host 4-54
HI initialization 4-42
host to DSP data transfer 4-49
polling/interrupt controlled data
transfer 4-45
interrupts 4-38
programming model 4-13 , 4-21
servicing protocols 4-37
usage considerations—DSP side 4-21
HI Command Interrupt Enable (HCIE) bit 4-15
HI Command Pending (HCP) bit 4-17
HI DMA bit 4-21
HI Flag 0 (HF0) bit 4-17
HI Flag 1 (HF1) bit 4-17
HI Flag 2 (HF2) bit 4-15
HI Flag 3 (HF3) bit 4-15
HI Pins
Host Enable (HEN) 4-35
host read/write (HR/W) 4-35
HI pins
Host Acknowledge (PB14/HACK) 4-36
Host Acknowledge pin (PB14/HACK) 4-36
Host Address pins (HOA0–HOA2) 4-35
Host Data Bus pins (H0–H7) 4-35
Host Request (PB13/HOREQ) 4-35
HI Receive Data Full (HRDF) bit 4-16
HI Receive data register (HORX) 4-18
HI Receive Interrupt Enable (HRIE) bit 4-15
HI registers after reset
as seen by DSP 4-19
HI Registers after Reset—DSP CPU Side 4-19
HI Transmit Data Empty (HTDE) bit 4-16
HI Transmit Interrupt Enable (HTIE) 4-15
HI08 2-10
HI
2
C (HCSR Serial Host Interface I
2
C/SPI
Selection) 5-13
HIDLE (HCSR Idle) 5-15
HI—Host Processor Data Transfer 4-37
HI—Host Processor Viewpoint 4-21
HM0-HM1 (HCSR Serial Host Interface
Mode) 5-14
HM1–HM0 bits 4-26
HMST (HCSR Master Mode) 5-14
HOA0–HOA2 pins 4-35
HOREQ 4-38
HOREQ bit 4-32
HOREQ pin 4-27 , 4-35
HOREQ signal 4-24
Host
Receive Data FIFO (HRX) 5-9
Receive Data FIFO—DSP Side 5-9
Transmit Data Register (HTX) 5-8
Transmit Data Register—DSP Side 5-8
Host Acknowledge pin (HACK) 4-36
Host Address pins (HOA0–HOA2) 4-35
Host Command bit (HC) 4-30
host command feature 4-22
Host Control Register (HCR) 4-14
Host Data Bus pins (H0–H7) 4-35
Host Flag 0 bit (HF0) 4-25
Host Flag 1 bit (HF1) 4-26
Host Flag 2 bit (HF2) 4-31
Host Flag 3 bit (HF3) 4-31
Host Flag operation 4-16
Host Interface 2-10 , 4-3 , 4-9
Host Interface (HI) 4-9