Motorola DSP56012 - Manual (Page 111)

Parallel Host Interface
Host Interface (HI)
MOTOROLA DSP56012 User’s Manual 4-31
4.4.5.6.2 ISR Transmit Data Register Empty (TXDE)—Bit 1
The Transmit Data Register Empty (TXDE) bit indicates that the Transmit byte
registers (TXH, TXM, and TXL) are empty and can be written by the host processor.
TXDE is set when the transmit byte registers are transferred to the HORX register.
TXDE is cleared when the Transmit byte Low (TXL) register is written by the host
processor. TXL is normally the last byte of the transmit byte registers to be written by
the host processor. TXDE can be set by the host processor using the initialize feature.
TXDE can be used to assert the external HOREQ pin if the TREQ bit is set. Regardless
of whether the TXDE interrupt is enabled, TXDE provides valid status so that polling
techniques can be used by the host processor.
Note: Hardware reset, software reset, individual reset, and Stop mode set TXDE.
4.4.5.6.3 ISR Transmitter Ready (TRDY)—Bit 2
The Transmitter Ready (TRDY) status bit indicates that both the TXH-TXM-TXL and
the HORX registers are empty.
TRDY = TXDE
•
HRDF
When TRDY is set, the data that the host processor writes to TXH, TXM, and TXL will
be immediately transferred to the DSP CPU side of the HI. This has many
applications. For example, if the host processor issues a host command that causes
the DSP CPU to read the HORX, the host processor can be guaranteed that the data it
just transferred to the HI is what is being received by the DSP CPU.
Note: Hardware reset, software reset, individual reset, and Stop mode set TRDY.
4.4.5.6.4 ISR HI Flag 2 (HF2)—Bit 3 (read only)
The HI Flag 2 (HF2) bit indicates the state of host flag 2 in the HCR. HF2 in the ISR
can only be changed by the DSP changing HF2 in the HCR (see
Figure 4-12
on page 4-26).
Note: HF2 is cleared by hardware reset and software reset.
4.4.5.6.5 ISR HI Flag 3 (HF3)—Bit 4 (read only)
The HI Flag 3 (HF3) bit indicates the state of host flag 3 in the HCR. HF3 in the ISR
can only be changed by the DSP changing HF3 in the HCR (see
Figure 4-12
on page 4-26).
Note: HF3 is cleared by hardware reset and software reset.
4.4.5.6.6 ISR Reserved—Bit 5
This bit is reserved for future expansion and will read as 0 during host processor read
operations.