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1 x and y data rom, 2 bootstrap rom, 3 dsp56012 data and program memory maps – Motorola DSP56012 User Manual

Page 64: X and y data rom -4, Bootstrap rom -4, Dsp56012 data and program memory maps -4

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3-4

DSP56012 User’s Manual

MOTOROLA

Memory, Operating Modes, and Interrupts

DSP56012 Data and Program Memory Maps

3.2.1

X and Y Data ROM

The X data ROM occupies locations $2000–$2DFF in the X memory space. The Y data
ROM occupies locations $2000–$27FF in the Y memory space.

3.2.2

Bootstrap ROM

The bootstrap ROM allows the user to use the on-chip pre-loaded Program ROM or
load a program into the first 256 words of Program RAM and use it for applications.
The bootstrap ROM occupies locations 0–31 ($0–$1F) in the DSP56012 memory map.
It is factory-programmed to perform the bootstrap operation following hardware
reset. The bootstrap ROM activity is controlled by the Mode A, Mode B, and Mode C
(MA, MB, and MC) bits in the Operating Mode Register (OMR). The bootstrap modes
are described in

Section

3.5

.

Basically, the user can configure the chip using the MOD pins (MODA, MODB, and
MODC), which are read and reflected by the mode bits. The mode selected by the
MOD pin/MOD bit values can select a bypass mode (Mode 4) that causes the DSP to
use the on-chip Program ROM, or one of three bootstrap modes (Modes 1, 5, and 7).
When in one of the three bootstrap modes, the first 256 words of Program RAM are
disabled for read but accessible for write, and the bootstrap routine loads up to 256
words into the reserved RAM space. The selected mode determines the method by
which the Program RAM is loaded:

• Parallel Host Interface (Mode 1)

• Serial Host Interface (SHI) using the SPI protocol (Mode 5)

• SHI using the I

2

C protocol (Mode 7)

Note:

The SHI operates in the Slave mode, with the 10-word FIFO enabled,
and with the HREQ pin enabled for receive operation.

The contents of the bootstrap ROM are provided in

Appendix A

.

3.3

DSP56012 DATA AND PROGRAM MEMORY MAPS

The memory in the DSP56012 can be mapped into four different configurations
according to the Program RAM Enable (PEA and PEB) bits in the OMR. Memory
maps for each of the four configurations are shown in Figure 3-1, Figure 3-2,
Figure 3-3

, and Figure 3-4, on the following pages.