Motorola DSP56012 - Manual (Page 270)

I-6 Motorola
HCSR
Bus Error 5-18
Host Busy 5-19
Host Receive FIFO Full 5-18
Host Receive FIFO Not Empty 5-18
Host Receive Overrun Error 5-18
Host Transmit Data Empty 5-17
Host Transmit Underrun Error 5-17
Receive Interrupt Enable 5-16
Master Mode 5-24
Slave Mode 5-23
SPI Data-To-Clock Timing 5-10
SPI Data-To-Clock Timing Diagram 5-10
SPI Mode 5-3
T
T0EN (TCS Transmitter 0 Enable) 6-17
T1EN (TCS Transmitter 1 Enable) 6-17
T2EN (TCS Transmitter 2 Enable) 6-18
TCKP (TCS Transmitter Clock Polarity) 6-19
TCS 6-22
TDIR (TCS Transmitter Data Shift Direction) 6-18
TDWE (TCS Transmitter Data Word
Expansion) 6-20
Timing Skew 1-12
TLDE (TCS Transmitter Left Data Empty) 6-22
TMST (TCS Transmitter Master) 6-18
Transmit Byte Registers (TXH, TXM, TXL) 4-33
Transmit Data Register Empty bit (TXDE) 4-31
Transmit Request Enable bit (TREQ) 4-24
Transmitter Ready bit (TRDY) 4-31
TRDE (TCS Transmitter Right Data Empty) 6-23
TRDY bit 4-31
TREL (TCS Transmitter Relative Timing) 6-20
TREQ bit 4-24
TWL0-TWL1 (TCS Transmitter Word Length
Control) 6-18
TX0, TX1 and TX2 (SAI Transmit Data
Registers) 6-23
TXDE bit 4-31
TXH register 4-33
TXIE (TCS Transmitter Interrupt Enable) 6-21
TXIL (TCS Transmitter Interrupt Location) 6-22
TXL register 4-33
TXM register 4-33
X
X Data Memory 1-15
Y
Y Data Memory 1-15