Motorola DSP56012 - Manual (Page 105)

Parallel Host Interface
Host Interface (HI)
MOTOROLA DSP56012 User’s Manual 4-25
In DMA modes, TREQ must be set or cleared by software to select the direction of
DMA transfers. Setting TREQ sets the direction of DMA transfer to be host to DSP
and enables the HOREQ pin to request data transfer.
Note: Hardware reset, software reset, individual reset, and Stop mode clear TREQ.
Table 4-2 summarizes the effect of RREQ and TREQ on the HOREQ pin.
4.4.5.3.3 ICR Reserved—Bit 2
This bit is reserved and unused, reads as 0 and should be written with 0 for
compatibility with future device revisions.
4.4.5.3.4 ICR HI Flag 0 (HF0)—Bit 3
The HI Flag 0 (HF0) bit is used as a general purpose flag for host-to-DSP
communication. HF0 can be set or cleared by the host processor and cannot be
changed by the DSP. HF0 is visible to the DSP as the read-only flag HF0 in the HSR
(see
Figure 4-9 on page 4-18).
Note: Hardware reset, software reset, individual reset, and Stop mode clear HF0.
Table 4-2 HOREQ Pin Definition
TREQ RREQ HOREQ Pin
Interrupt Mode
0 0 No Interrupts (Polling)
0 1 RXDF Request (Interrupt)
1 0 TXDE Request (Interrupt)
1 1 RXDF and TXDE Request
(Interrupts)
DMA Mode
0 0 No DMA
0 1 DSP to Host Request (RX)
1 0 Host to DSP Request (TX)
1 1 Undefined (Illegal)