Motorola DSP56012 - Manual (Page 119)

Parallel Host Interface
Host Interface (HI)
MOTOROLA DSP56012 User’s Manual 4-39
5. DMA = 1, signifying the HI is currently being used for DMA transfers; if DMA
transfers are possible in the system, deactivate HACK prior to reading the ISR
so both DMA data and the contents of ISR are not simultaneously output on
H0–H7.
6. If HOREQ = 1, the HOREQ pin has been asserted, and one of the previous five
conditions exists.
Generally, after the appropriate data transfer has been made, the corresponding
status bit will toggle.
If the host processor has issued a command to the DSP by writing the CVR and
setting the HC bit, it can read the HC bit in the CVR to determine when the command
has been accepted by the interrupt controller in the DSP’s central processing module.
When the command has been accepted for execution, the interrupt controller will
reset the HC bit.
4.4.7.4 Servicing Non-DMA Interrupts
When HM0 = HM1 = 0 (non-DMA) and HOREQ is connected to the host processor
interrupt input, the HI can request service from the host processor by asserting
HOREQ. In the non-DMA mode, HOREQ will be asserted when TXDE = 1 and/or
RXDF = 1 and the corresponding mask bit (TREQ or RREQ) is set. This is illustrated
in
Figure 4-16 .
Generally, servicing the interrupt starts with reading the ISR, as described in the
previous section on polling, to determine which DSP has generated the interrupt and
why. When multiple DSPs occur in a system, the HOREQ bit in the ISR will normally
be read first to determine the interrupting device. The host processor interrupt
service routine must read or write the appropriate HI register to clear the interrupt.
HOREQ is deasserted when the enabled request is cleared or masked.
In the case where the host processor is a member of the MC680XX family, servicing
the interrupt will start by asserting HOREQ to interrupt the processor (see
Figure 4-17 ). The host processor then acknowledges the interrupt by asserting
HACK. While HOREQ and HACK are simultaneously asserted, the contents of the
IVR are placed on the host data bus. This vector will tell the host processor which
routine to use to service the HOREQ interrupt.
The HOREQ pin is an open-drain output pin so that it can be wire-ORed with the
HOREQ pins from other DSP56012 processors in the system. When the DSP56012
generates an interrupt request, the host processor can poll the HOREQ bit in the ISR
of each of the connected DSPs to determine which device generated the interrupt.