Motorola DSP56012 - Manual (Page 193)

Serial Audio Interface
Serial Audio Interface Programming Model
MOTOROLA DSP56012 User’s Manual 6-15
6.3.2.11 RCS Receiver Interrupt Enable (RXIE)—Bit 11
When the read/write Receiver Interrupt Enable (RXIE) control bit is set, receiver
interrupts for both left and right data words are enabled, and the DSP is interrupted
if either the RLDF or RRDF status bit is set. When RXIE is cleared, receiver interrupts
are disabled, however, RLDF and RRDF bits still indicate the receive data register full
conditions and can be polled for status. Note that clearing RXIE will mask a pending
receiver interrupt only after a one-instruction-cycle delay. If RXIE is cleared in a long
interrupt service routine, it is recommended that at least one other instruction should
be inserted between the instruction that clears RXIE and the RTI instruction at the
end of the interrupt service routine.
There are three different receive data interrupts that have separate interrupt vectors:
1. Left Channel Receive interrupt is generated when RXIE = 1, RLDF = 1, and
RRDF = 0.
2. Right Channel Receive interrupt is generated when RXIE = 1, RLDF = 0, and
RRDF = 1.
3. Receive interrupt with exception (overrun) is generated when RXIE = 1,
RLDF = 1, and RRDF = 1. This means that the previous data in the receive data
register was lost and an overrun occurred.
To clear RLDF or RRDF during Left or Right channel interrupt service, the receive
data registers of the enabled receivers must be read. Clearing RLDF or RRDF will
clear the respective interrupt request. If the “Receive interrupt with exception”
indication is signaled (RLDF = RRDF = 1), then RLDF and RRDF are both cleared by
reading the RCS register, followed by reading the receive data register of the enabled
receivers.
Note: Receivers 0 and 1 share the same controller. This means that the enabled
receivers will be operating in parallel and any interrupt signaled will indicate
a condition on all enabled receive data registers. The RXIE bit is cleared
during hardware reset and software reset.
6.3.2.12 RCS Receiver Interrupt Location (RXIL)—Bit 12
The read/write Receiver Interrupt Location (RXIL) control bit determines the
location of the receiver interrupt vectors. When RXIL = 0, the Left Channel Receiver,
the Right Channel Receiver and the Receiver Exception interrupt vectors are located
in program addresses $16, $18, and $1A, respectively. When RXIL = 1, the Left
Channel Receiver, the Right Channel Receiver and the Receiver Exception interrupt
vectors are located in program addresses $46, $48, and $4A, respectively. The RXIL
bit is cleared during hardware reset and software reset. Refer to Table 6-1
on page 6-9.