Motorola DSP56012 User Manual
Page 243
Programming Reference
MOTOROLA
DSP56012 User’s Manual
B-11
MAC
(+)S2,S1,D
(parallel move)
1+mv
2+mv
* * * * * * * -
(+)S1,S2,D
(parallel move)
(+)S,#n,D
(no parallel move)
1
2
MACR
(+)S2,S1,D
(parallel move)
1+mv
2+mv
* * * * * * * -
(+)S1,S2,D
(parallel move)
(+)S,#n,D
(no parallel move)
1
2
MOVE
S,D
1+mv
2+mv
* * - - - - - -
No parallel data move
(.....)
mv
mv
- - - - - - - -
Immediate short
(.....)#xx,D
mv
mv
- - - - - - - -
data move
Register to register
(.....)S,D
mv
mv
* * - - - - - -
data move
Address register update
(.....)ea
mv
mv
- - - - - - - -
X memory data move
(.....)X:
mv
mv
* * - - - - - -
(.....)X:
(.....)S,X:
(.....)S,X:
(.....)#xxxxxx,D
Register and X memory
data move
(.....)X:
S2,D2
mv
mv
* * - - - - - -
(.....)S1,X:
S2,D2
(.....)#xxxxxx,D1
S2,D2
(.....)A,X:
X0,A
(.....)B,X:
X0,B
Y memory data move
(.....)Y:
mv
mv
* * - - - - - -
(.....)Y:
(.....)S,Y:
(.....)S,Y:
(.....)#xxxxxx,D
Table B-3
Instruction Set Summary (Sheet 4 of 7)
Mnemonic
Syntax
Parallel Moves
Instruction
Program
Words
Osc.
Clock
Cycles
Status Request
Bits:
S L E U N Z V C
- indicates that the bit is unaffected by the operation
* indicates that the bit may be set according to the definition, depending on parallel move conditions
? indicates that the bit is set according to a special definition; see the instruction descriptions in Appendix A of
the
DSP56000 Family Manual (DSP56KFAMUM/AD)
0 indicates that the bit is cleared