Motorola DSP56012 - Manual (Page 219)

Digital Audio Transmitter
DAX Internal Architecture
MOTOROLA DSP56012 User’s Manual 8-9
8.5.4.4 DAX Clock Input Select (XCS[1:0])—Bits 3–4
The XCS[1:0] bits select the source of the DAX clock and/or its frequency. Table 8-3
shows the configurations selected by these bits. These bits should be changed only
when the DAX is disabled.
Note: The XCS bits are cleared by software reset and hardware reset.
8.5.4.5 XCTR Reserved Bits—Bits 5-9, 16-23
These XCTR bits are reserved and unused. They read as 0s and should be written
with 0s for future compatibility.
8.5.4.6 DAX Channel A Validity (XVA)—Bit 10
The value of the XVA bit is transmitted as the twenty-ninth bit (Bit 28) of Channel A
sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.
8.5.4.7 DAX Channel A User Data (XUA)—Bit 11
The value of the XUA bit is transmitted as the thirtieth bit (Bit 29) of the Channel A
sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.
8.5.4.8 DAX Channel A Channel Status (XCA)—Bit 12
The value of the XCA bit is transmitted as the thirty-first bit (Bit 30) of the Channel A
sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.
8.5.4.9 DAX Channel B Validity (XVB)—Bit 13
The value of the XVB bit is transmitted as the twenty-ninth bit (Bit 28) of the Channel
B sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.
Table 8-3 Clock Source Selection
XCS1 XCS0 DAX Clock Source
0 0 DSP Core Clock (f = 1024
×
fs)
0 1 ACI Pin, f = 256
×
fs
1 0 ACI Pin, f = 384
×
fs
1 1 ACI Pin, f = 512
×
fs