Motorola DSP56012 - Manual (Page 165)

Serial Host Interface
Serial Host Interface Programming Model
MOTOROLA DSP56012 User’s Manual 5-17
Note: HRIE[1:0] are cleared by hardware and software reset.
Note: Clearing HRIE[1:0] will mask a pending receive interrupt only after a
one-instruction-cycle delay. If HRIE[1:0] are cleared in a long interrupt service
routine, it is recommended that at least one other instruction separate the
instruction that clears HRIE[1:0] and the RTI instruction at the end of the
interrupt service routine.
5.4.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 14
The read-only status bit Host Transmit Underrun Error (HTUE) indicates that a
transmit-underrun error occurred. Transmit-underrun errors can occur only when
operating in a Slave mode (in a Master mode, transmission takes place on demand
and no underrun can occur). It is set when both the shift register and the HTX
register are empty and the external master begins reading the next word:
• When operating in the I
2
C mode, HTUE is set in the falling edge of the ACK
bit. In this case, the SHI will retransmit the previously transmitted word.
• When operating in the SPI mode, HTUE is set at the first clock edge if
CPHA = 1; it is set at the assertion of SS if CPHA = 0.
If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt vector
will be generated. If a transmit interrupt occurs with HTUE cleared, the regular
transmit-data interrupt vector will be generated. HTUE is cleared by reading the
HCSR and then writing to the HTX register. HTUE is cleared by hardware reset,
software reset, SHI individual reset, and during the Stop state.
5.4.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15
The read-only status bit Host Transmit Data Empty (HTDE) indicates that the HTX
register is empty and can be written by the DSP. HTDE is set when the data word is
transferred from HTX to the shift register, except for a special case in SPI Master
mode when CPHA = 0 (see HCKR). When operating in the SPI Master mode with
Table 5-6 HCSR Receive Interrupt Enable Bits
HRIE[1:0] Interrupt Condition
00 Disabled Not applicable
01 Receive FIFO not empty
Receive Overrun Error HRNE = 1 and HROE = 0
HROE = 1
10 Reserved Not applicable
11 Receive FIFO full
Receive Overrun Error HRFF = 1 and HROE = 0
HROE = 1