Index – Motorola DSP56012 User Manual
Page 265
Index
Motorola
I-1
A
Address Buses
Address Generation Unit
AES/EBU
B
bootstrap loading using the HI
Bootstrap Program Listing
A-4
bootstrap ROM
Bootstrap ROM — See Appendix A
C
CDP Format
Clock
Command Vector Register (CVR)
CP-340
CPHA and CPOL (HCKR Clock Phase and
Polarity Controls)
CVR register
bit 0–5—Host Vector bits (HV)
bit 6—reserved
bit 7—Host Command bit (HC)
D
Data ALU
Data Buses
data transfer
DMA
DSP to host
host to DSP
polling/interrupt controlled
DAX
Block Transferred Interrupt Handling
Initiating A Transmit Session
Transmit Register Empty Interrupt
Handling
DAX Audio Data register Empty (XADE) status
flag
DAX Audio Data Registers (XADRA/XADRB)
DAX Audio Data Shift Register (XADSR)
DAX biphase encoder
DAX Block transfer (XBLK) flag
DAX Channel A Channel status (XCA) bit
DAX Channel A User data (XUA) bit
DAX Channel A Validity (XVA) bit
DAX Channel B Channel Status (XCB) bit
DAX Channel B User Data (XUB) bit
DAX Channel B Validity (XVB) bit
DAX Clock input Select bits
DAX clock multiplexer
DAX clock selection
DAX Control Register (XCTR)
DAX Enable (XEN) bit
DAX internal architecture
DAX Interrupt Enable (XIEN) bit
DAX Non-Audio Data Buffer (XNADBUF)
DAX Operation During Stop
DAX Parity Generator (PRTYG)
DAX preamble generator
DAX Preamble sequence
DAX Programming Considerations
DAX programming model
DAX Status Register (XSTR)
DAX Stop control (XSTP) bit
DAX Transmit In Progress (XTIP) status flag
DAX Transmit Underrun error (XAUR) status
flag
Digital Audio Transmitter (DAX)
DMA bit
DMA mode
DMA procedure
DSP to host
host to DSP
DMA Status bit (DMA)
DSP to host
DMA procedure
internal processing
DSP56011 Features
F
Frequency Multiplication by the PLL
G
GC0-GC3 (GPIOR Control Bits)
GD0-GD3 (GPIOR Data Bits)
GDD0-GDD3 (GPIOR Data Direction Bits)
General Purpose I/O — See Section 7
General Purpose I/O (GPIO)
General Purpose Input/Output (GPIO)
GPIO