Motorola DSP56012 - Manual (Page 109)

Parallel Host Interface
Host Interface (HI)
MOTOROLA DSP56012 User’s Manual 4-29
counter is not automatically updated, and, as a result, the DMA counter will point to
the wrong data register immediately after HM1 and HM0 are changed. The INIT
function must be used to correctly preset the internal DMA counter. Always set INIT
after changing HM0 and HM1. However, the DMA counter can not be initialized in
the middle of a DMA transfer. Even though the INIT bit is set, the internal DMA
controller will wait until after completing the data transfer in progress before
executing the initialization.
4.4.5.5 Command Vector Register (CVR)
The host processor uses the Command Vector Register (CVR) to cause the DSP to
execute a vectored interrupt. The host command feature is independent of the data
transfer mechanisms in the HI. It can be used to cause any of the sixty-four possible
interrupt routines in the DSP CPU to be executed. The command vector register is
shown in
Figure 4-13 .
4.4.5.5.1 CVR HI Vector (HV)—Bits 0–5
The six HI Vector (HV) bits select the host command interrupt address to be used by
the host command interrupt logic. When the host command interrupt is recognized
by the DSP interrupt control logic, the starting address of the interrupt taken is 2
×
HV. The host can write HC and HV in the same write cycle, if desired.
The host processor can select any of the sixty-four possible interrupt routine starting
addresses in the DSP by writing the chosen interrupt routine starting address,
divided by 2, into HV[5:0]. This means that the host processor can force any of the
existing DSP interrupt handlers (SAI, SHI, DAX, IRQA, IRQB, etc.) and can use any
of the reserved or otherwise unused starting addresses provided they have been
preprogrammed in the DSP. HV is set to $17 (vector location $0034) by hardware
reset, software reset, individual reset, and Stop mode.
Note: The HV should not be used with a value of 0 because the reset location is
normally programmed with a JMP instruction. Doing so will cause an
improper fast interrupt.
Figure 4-13 Command Vector Register
HV1 HV0 HV2 HV3 HV4 HV5
*
HC
0 7 6 5 4 3 2 1
AA0321k
Host Vector
Reserved
Host Command
Command Vector Register (CVR)