6 hcr reserved—bits 5, 6, and 7, 2 hi status register (hsr), 1 hsr hi receive data full (hrdf)—bit 0 – Motorola DSP56012 User Manual
Page 96: 2 hsr hi transmit data empty (htde)—bit 1, Hcr reserved—bits 5, 6, and 7 -16, Hi status register (hsr) -16, Hsr hi receive data full (hrdf)—bit 0 -16, Hsr hi transmit data empty (htde)—bit 1 -16
6 hcr reserved—bits 5, 6, and 7, 2 hi status register (hsr), 1 hsr hi receive data full (hrdf)—bit 0 | 2 hsr hi transmit data empty (htde)—bit 1, Hcr reserved—bits 5, 6, and 7 -16, Hi status register (hsr) -16, Hsr hi receive data full (hrdf)—bit 0 -16, Hsr hi transmit data empty (htde)—bit 1 -16 | Motorola DSP56012 User Manual | Page 96 / 270