4 operating mode register (omr), Figure35 operating mode register (omr), 1 dsp operating mode (mc, mb, ma)—bits 4, 1, and 0 – Motorola DSP56012 User Manual
Page 72: 3 stop delay (sd)—bit 6, Operating mode register (omr) -12, Stop delay (sd)—bit 6 -12, Figure 3-5, Operating mode register (omr) -11, Program ram enable a (pea)—bit 2 -11
4 operating mode register (omr), Figure35 operating mode register (omr), 1 dsp operating mode (mc, mb, ma)—bits 4, 1, and 0 | 3 stop delay (sd)—bit 6, Operating mode register (omr) -12, Stop delay (sd)—bit 6 -12, Figure 3-5, Operating mode register (omr) -11, Program ram enable a (pea)—bit 2 -11 | Motorola DSP56012 User Manual | Page 72 / 270