Table54 shi data size, 4 hcsr reserved bits—bits 23, 18, 16, and 4, 5 hcsr fifo-enable control (hfifo)—bit 5 – Motorola DSP56012 User Manual
Page 162: 6 hcsr master mode (hmst)—bit 6, Hcsr reserved bits—bits 23, 18, 16, and 4 -14, Hcsr fifo-enable control (hfifo)—bit 5 -14, Hcsr master mode (hmst)—bit 6 -14, Table 5-4, Shi data size -14
Table54 shi data size, 4 hcsr reserved bits—bits 23, 18, 16, and 4, 5 hcsr fifo-enable control (hfifo)—bit 5 | 6 hcsr master mode (hmst)—bit 6, Hcsr reserved bits—bits 23, 18, 16, and 4 -14, Hcsr fifo-enable control (hfifo)—bit 5 -14, Hcsr master mode (hmst)—bit 6 -14, Table 5-4, Shi data size -14 | Motorola DSP56012 User Manual | Page 162 / 270