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3 shi host receive data fifo (hrx)—dsp side, 4 shi slave address register (hsar)—dsp side, 1 hsar reserved bits—bits 17–0,19 – Motorola DSP56012 User Manual

Page 157: 5 shi clock control register (hckr)—dsp side, Shi host receive data fifo (hrx)—dsp side -9, Shi slave address register (hsar)—dsp side -9, Hsar reserved bits—bits 17–0,19 -9, Hsar i, Shi clock control register (hckr)—dsp side -9

3 shi host receive data fifo (hrx)—dsp side, 4 shi slave address register (hsar)—dsp side, 1 hsar reserved bits—bits 17–0,19 | 5 shi clock control register (hckr)—dsp side, Shi host receive data fifo (hrx)—dsp side -9, Shi slave address register (hsar)—dsp side -9, Hsar reserved bits—bits 17–0,19 -9, Hsar i, Shi clock control register (hckr)—dsp side -9 | Motorola DSP56012 User Manual | Page 157 / 270 3 shi host receive data fifo (hrx)—dsp side, 4 shi slave address register (hsar)—dsp side, 1 hsar reserved bits—bits 17–0,19 | 5 shi clock control register (hckr)—dsp side, Shi host receive data fifo (hrx)—dsp side -9, Shi slave address register (hsar)—dsp side -9, Hsar reserved bits—bits 17–0,19 -9, Hsar i, Shi clock control register (hckr)—dsp side -9 | Motorola DSP56012 User Manual | Page 157 / 270
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