Maxq610 user’s guide – Maxim Integrated MAXQ610 User Manual
Page 99
6-6
MAXQ610 User’s Guide
Bits 7:0: Input/Output Direction for Port 0. The bits in this register control the input/output direction for port pins P0 .0
to P0 .7 . When PD0 .n is set to 0, the corresponding port pin (P0 .n) acts as an input with characteristics determined by
PO0 .n . When PD0 .n is set to 1, the port pin acts as an output, driving the output state given by PO0 .n .
Bits 7:0: Input/Output Direction for Port 1. The bits in this register control the input/output direction for port pins P1 .0
to P1 .7 . When PD1 .n is set to 0, the corresponding port pin (P1 .n) acts as an input with characteristics determined by
PO1 .n . When PD1 .n is set to 1, the port pin acts as an output, driving the output state given by PO1 .n .
Bits 7:0: Input/Output Direction for Port 2. The bits in this register control the input/output direction for port pins P2 .0
to P2 .7 . When PD2 .n is set to 0, the corresponding port pin (P2 .n) acts as an input with characteristics determined by
PO2 .n . When PD2 .n is set to 1, the port pin acts as an output, driving the output state given by PO2 .n .
Bits 7:0: Input/Output Direction for Port 3. The bits in this register control the input/output direction for port pins P3 .0
to P3 .7 . When PD3 .n is set to 0, the corresponding port pin (P3 .n) acts as an input with characteristics determined by
PO3 .n . When PD3 .n is set to 1, the port pin acts as an output, driving the output state given by PO3 .n .
Register Name
PD0
Register Description
Port 0 Direction Register
Register Address
M0[10h]
Register Name
PD1
Register Description
Port 1 Direction Register
Register Address
M0[11h]
Register Name
PD2
Register Description
Port 2 Direction Register
Register Address
M0[12h]
Register Name
PD3
Register Description
Port 3 Direction Register
Register Address
M0[13h]
Bit #
7
6
5
4
3
2
1
0
Name
PD0 .7
PD0 .6
PD0 .5
PD0 .4
PD0 .3
PD0 .2
PD0 .1
PD0 .0
Reset
s
s
s
s
s
s
s
s
Access
rw
rw
rw
rw
rw
rw
rw
rw
Bit #
7
6
5
4
3
2
1
0
Name
PD1 .7
PD1 .6
PD1 .5
PD1 .4
PD1 .3
PD1 .2
PD1 .1
PD1 .0
Reset
s
s
s
s
s
s
s
s
Access
rw
rw
rw
rw
rw
rw
rw
rw
Bit #
7
6
5
4
3
2
1
0
Name
PD2 .7
PD2 .6
PD2 .5
PD2 .4
PD2 .3
PD2 .2
PD2 .1
PD2 .0
Reset
s
s
s
s
s
s
s
s
Access
rw
rw
rw
rw
rw
rw
rw
rw
Bit #
7
6
5
4
3
2
1
0
Name
PD3 .7
PD3 .6
PD3 .5
PD3 .4
PD3 .3
PD3 .2
PD3 .1
PD3 .0
Reset
s
s
s
s
s
s
s
s
Access
rw
rw
rw
rw
rw
rw
rw
rw