Maxim Integrated MAXQ610 - Manual (Page 143)

10-7
MAXQ610 User’s Guide
Bit 3: Mode Fault Flag (MODF). This bit is the mode fault flag for SPI master mode operation . When mode fault detec-
tion is enabled (MODFE = 1) in master mode, detection of high to low transition on the SSEL pin signifies a mode fault
causes MODF to be set to 1 . This bit must be cleared to 0 by software once set . Setting this bit to 1 causes an interrupt
if enabled . This flag has no meaning in slave mode .
0 = No mode fault has been detected
1 = Mode fault detected while operating as a master (MSTM = 1)
Bit 2: Mode Fault Enable (MODFE). When set to 1, the SSEL input pin is used for mode fault detection during SPI
master mode operation . When cleared to 0, the SSEL input has no function and its pin can be used for general-purpose
I/O . In slave mode, the SSEL pin always functions as a slave-select input signal to the SPI module, independent of the
setting of the MODFE bit .
Bit 1: Master Mode Enable (MSTM). The MSTM bit functions as a master mode enable bit for the SPI module .
0 = SPI module operates in slave mode when enabled (SPIEN = 1)
1 = SPI module operates in master mode when enabled (SPIEN = 1)
Note that this bit can be set from 0 to 1 only when the SSEL signal is deasserted . This bit can be automatically cleared
to 0 by hardware if a mode fault is detected .
Bit 0: SPI Enable (SPIEN)
0 = SPI module and its baud-rate generator are disabled
1 = SPI module and its baud-rate generator are enabled
10.8.2 SPI Configuration Register (SPICF)
Bit 7: SPI Interrupt Enable (ESPII). This bit enables any of the SPI interrupt source flags (MODF, WCOL, ROVR, SPIC)
to generate interrupt requests .
0 = SPI interrupt sources disabled
1 = SPI interrupt sources enabled
Bit 6: SPI Slave Active Select (SAS). This bit selects SSEL asserted state .
0 = SSEL is active low
1 = SSEL is active high
Bit 2: Character Length Bit (CHR). This bit determines the character length for a SPI transfer cycle . A character can
be 8 bits in length or 16 bits in length .
0 = 8-bit character length specified
1= 16-bit character length specified
Bit 1: Clock Phase Select (CKPHA). This bit selects the clock phase and is used in conjunction with the CKPOL bit
to define the SPI data transfer format .
0 = data sampled on the active clock edge
1 = data sampled on the inactive clock edge
Bit 0: Clock Polarity Select (CKPOL). This bit selects the clock polarity and is used in conjunction with the CKPHA
bit to define the SPI data transfer format .
0 = clock idles in the 0 state (rising = active clock edge)
1 = clock idles in the 1 state (falling = active clock edge)
7 0
— — — SPI Configuration Register (SPICF)
0 0 0 0 0 0 0 0 Power-On Reset and System Resets
rw rw r r r rw rw rw Read (r), Write (w), or Special (s) access