Maxim Integrated MAXQ610 - Manual (Page 84)

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MAXQ610 User’s Guide
REGISTER DESCRIPTION
TB0CN (01h, 02h) Timer B 0 Control Register (16-bit register)
Initialization: This register is cleared to 0000h on all forms of reset .
Read/Write Access: Unrestricted read/write .
TB0CN.0 (CP/RLB) Capture/Reload Select. This bit determines whether the capture or reload function is used
for Timer B . Timer B functions in an autoreload mode following each overflow/underflow .
See the TFB bit description for overflow/underflow condition . Setting this bit to 1 causes a
Timer B capture to occur when a falling edge is detected on TBB if EXENB is 1 . Clearing
this bit to 0 causes an autoreload to occur when Timer B overflow or a falling edge is
detected on TBB if EXENB is 1 . It is not intended that the Timer B compare functionality
should be used when operating in capture mode .
TB0CN.1 (ETB) Enable Timer B Interrupt. Setting this bit to 1 enables the interrupt from the Timer B TFB
and EXFB flags in TBCN . In Timer B clock output mode (TBOE = 1), the timer overflow flag
(TFB) is still set on an overflow, however, the TBOE = 1 condition prevents this flag from
causing an interrupt when ETB = 1 .
TB0CN.2 (TRB) Timer B Run Control. This bit enables Timer B operation when set to 1 . Clearing this bit to
0 halts Timer B operation and preserves the current count in TBV .
TB0CN.3 (EXENB) Timer B External Enable. Setting this bit to 1 enables the capture/reload function on the
TBB pin for a negative transition (in up-counting mode) . A reload results in TBV being
reset to 0000h . Clearing this bit to 0 causes Timer B to ignore all external events on TBB
pin . When operating in autoreload mode (CP/RLB = 0) with the PWM output functionality
enabled, enabling the TBB input function (EXENB = 1) allows PWM output negative transi-
tions to set the EXFB flag, however, no reload occurs as a result of the external negative
edge detection .
TB0CN.4 (DCEN) Down-Count Enable. This bit in conjunction with the TBB pin controls the direction that
Timer B counts in 16-bit autoreload mode . Clearing this bit to 0 causes Timer B to count
up only . Setting this bit to 1 enables the up/down-counting mode (i .e ., it causes Timer B
to count up if the TBB pin is 1 and to count down if the TBB pin is 0) . When Timer B PWM
output mode functionality is enabled along with up/down counting (DCEN = 1), the up/
down-count control of Timer B is controlled internally based upon the count in relation to the
register settings . In the compare modes, the DCEN bit controls whether the timer counts up
and resets (DCEN = 0), or counts up and down (DCEN = 1) .