Maxim Integrated MAXQ610 - Manual (Page 34)

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MAXQ610 User’s Guide
Power-management mode is invoked by setting the PMME bit to 1 . Once this bit has been set, one system clock cycle
occurs every 256 oscillator cycles . All operations continue as normal in this mode, but at the reduced clock rate . Power-
management mode can be deactivated by clearing the PMME bit to 0; the PMME bit is also cleared automatically to
0 by any reset condition .
To avoid data loss, the PMME bit cannot be set while the USART or SPI ports are either transmitting or receiving, or
while an external interrupt is waiting to be serviced . Attempts to set the PMME bit under these conditions result in a
no-op .
2.12.1 Switchback
When power-management mode is active, the MAXQ610 operates at a reduced clock rate . Although execution contin-
ues as normal, peripherals that base their timing on the system clock such as the USART module and the SPI module
might be unable to operate normally or at a high enough speed for proper application response . Additionally, interrupt
latency is greatly increased .
The switchback feature is used to allow a processor running under power-management mode to switch back to normal
mode quickly under certain conditions that require rapid response . Switchback is enabled by setting the SWB bit to 1 .
If switchback is enabled, a processor running under power-management mode automatically clears the PMME bit to
0 and returns to normal mode when any of the following conditions occur:
• An external interrupt condition occurs on an INTn pin and the corresponding external interrupt is enabled.
• An active-low transition occurs on the USART serial receive input line (modes 1, 2, and 3) and data reception is
enabled .
• The SBUF register is written to send an outgoing byte through the USART and transmission is enabled.
• The SPIB register is written in master mode (STBY = 1) to send an outgoing character through the SPI module and
transmission is enabled .
• The SPI module’s SSEL signal is asserted in slave mode .
• Active debug mode is entered either by breakpoint match or issuance of the debug command from background
mode .
• Power-fail interrupt if enabled (PFIE = 1).
2.13 Stop Mode
When the MAXQ610 is in stop mode, the CPU system clock is stopped and all processing activity is halted . All on-chip
peripherals requiring the system clock are also stopped . Power consumption in the lowest power stop mode is basi-
cally limited to static leakage current .
Stop mode is entered by setting the STOP bit to 1 . The processor enters stop mode immediately once the instruction
that sets the STOP bit is executed .
Note: It is necessary to include a ‘nop’ immediately following the instruction to invoke stop mode for proper interrupt
operation . Example code is as follows:
move ckcn, #010h ; enter stop mode
nop ; No operation to cause a one cycle delay
The MAXQ610 exits stop mode when any of the following conditions occur:
• An external interrupt condition occurs on one of the INTn pins and the corresponding external interrupt is enabled.
After the interrupt returns, execution resumes after the stop point .
• An external reset signal is applied to the RESET pin . After the reset signal is removed, execution resumes from utility
ROM at 8000h as it would after any reset state .
• A power-fail interrupt occurs, if enabled (PFIE = 1).
• A wake-up timer interrupt occurs, if enabled (WTE = 1).