Maxim Integrated MAXQ610 - Manual (Page 163)

12-12
MAXQ610 User’s Guide
Bit 5: Break-On Register Enable (REGE). The REGE bit is used to enable the break on register function . When REGE
bit is set to 1, BP4 and BP 5 are used as register breakpoints . A break occurs when the content of BP4 is matched with
the destination address of the current instruction . For BP5, a break occurs only on a selected data pattern for a selected
destination register addressed by BP5 . The data pattern is determined by the contents in the ICDA and ICDD register .
The REGE bit alone does not enable register breakpoints, but simply changes the manner in which BP4, BP5 are used .
The DME bit still must be set to a logic 1 for any breakpoint to occur . This bit has no meaning for the utility ROM code .
Bits 3:0: Command Bits (CMD[3:0]). These bits reflect the current host command in debug mode . These bits are set
by the debug engine and allow the utility ROM code to determine the course of action .
12.4.3 In-Circuit Debug Flag Register (ICDF)
Bits 3:2: Programming Source Select Bits 1:0 (PSS[1:0]). These bits are used to select a programming interface
during in-system programming when SPE is set to 1 . Otherwise, the logic values of these bits have no meaning . The
logical states of these bits, when read by the CPU, reflect the logical-OR of the PSS bits that are write accessible by
the CPU and those in the system programming buffer (SPB) register of the TAP module (which are accessible through
JTAG) . These bits are read/write accessible for the CPU and are cleared to 0 by a power-on reset or test-logic-reset .
CPU writes to the PSS bits result in clearing of the JTAG PSS[1:0] bits .
Bit 1: System Program Enable (SPE). The SPE bit is used for in-system programming support and its logical state,
when read by the CPU, always reflects the logical-OR of the SPE bit that is write accessible by the CPU and the SPE
bit of the system programming buffer (SPB) register in the TAP module (which is accessible through JTAG) . The logical
state of this bit determines the program flow after a reset . When it is set to 1, in-system programming is executed by
the utility ROM . When it is cleared to 0, execution is transferred to user code . This bit allows read/write access by the
CPU and is cleared to 0 only on a power-on reset or test-logic-reset . The JTAG SPE bit is cleared by hardware when
the ROD bit is set . CPU writes to the SPE bit result in the clearing of the JTAG PSS[1:0] bits .
Bit 0: Serial Transfer Complete (TXC). This bit is set by hardware at the end of a transfer cycle at the TAP com-
munication link . The TXC bit helps the debug engine to recognize host requests, either command or data . This bit is
normally set by utility ROM code to signify or request the sending or receiving of data . The TXC bit is cleared by the
debug engine once set . CPU writes to the TXC bit results in the clearing of the JTAG PSS[1:0] bits .
CMD[3:0] ACTION
0000 No operation
0001 Read register map
0010 Read data memory
0011 Read stack memory
0100 Write register
0101 Write data memory
1000 Unlock password
1001 Read register
Other Reserved
7 0
— — — — In-Circuit Debug Flag Register (ICDF)
0
r
0
r
0
r
0
r
0
rw
0
rw
0
rw
0
rw
Power-On Reset and Test-Logic-Reset
Read (r), Write (w), or Special (s) access
PSS1 PSS0 SOURCE SELECTION
0 0 JTAG
Others Reserved